Internal Use Only North/Latin America Europe/Africa Asia/Oceania http://aic.lgservice.com http://eic.lgservice.com http://biz.lgservice.com PLASMA TV SERVICE MANUAL CHASSIS : PA21A MODEL : 60PA6500 60PA6500-TF CAUTION BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL. P/NO : MFL67444303 (1112-REV00) Downloaded from www.Manualslib.com manuals search engine Printed in Korea CONTENTS CONTENTS . ............................................................................................. 2 SAFETY PRECAUTIONS ......................................................................... 3 SPECIFICATION........................................................................................ 4 ADJUSTMENT INSTRUCTION................................................................. 6 BLOCK DIAGRAM................................................................................... 13 EXPLODED VIEW .................................................................................. 14 SCHEMATIC CIRCUIT DIAGRAM .............................................................. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine -2- LGE Internal Use Only SAFETY PRECAUTIONS IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. General Guidance Leakage Current Hot Check (See below Figure) Plug the AC cord directly into the AC outlet. An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks. It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation. If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified. When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB. Keep wires away from high voltage or high temperature parts. Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to 0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer. Leakage Current Hot Check circuit AC Volt-meter Before returning the receiver to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock. Leakage Current Cold Check(Antenna Cold Check) With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine -3- To Instrument's exposed METALLIC PARTS 0.15u Good Earth Ground such as WATER PIPE, CONDUIT etc. 1.5 Kohm/10W LGE Internal Use Only SPECIFICATION NOTE : Specifications and others are subject to change without notice for improvement. 1. Application range This spec sheet is applied all of the PDP TV with PA21A chassis. 2. Requirement for Test Each part is tested as below without special appointment. (1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C (2) Relative Humidity: 65 % ± 10 % (3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models. (4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. (5) The receiver must be operated for about 5 minutes prior to the adjustment. 3. Test method (1) Performance: LGE TV test method followed (2) Demanded other specification - Safety : CE, IEC specification - EMC : CE, IEC 4. Module General Specification - 60" 2D FHD No Item Specification Remark 1 Display Screen Device 152 cm (60 inch) wide Color Display Module PDP 2 Aspect Ratio 16:9 3 PDP Module PDP60R4####, RGB Closed (Well) Type, Glass Filter (38%) Pixel Format: 1920 horiz. By 1080 ver. 4 Operating Environment 5) Temp. : 0 ~ 40 deg 6) Humidity : 20 ~ 80% 5 Storage Environment 7) Temp. : -20 ~ 60 deg 8) Humidity : 10 ~ 90 % 6 Input Voltage AC100 ~ 240V, 50/60Hz Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE SPEC Maker LG -4- LGE Internal Use Only 5. Model General Specification No Item Specification 1 Market Australia, New Zealand, Indonesia, Malaysia, Singapore, South Africa, Israel, Iran, Vietnam, Myanmar, Non-EU analog 2 Broadcasting system 1) PAL/SECAM BG 2) PAL/SECAM DK 3) PAL I / II 4) SECAM L/L’ 5) DVB T 6) DVB C 3 Receiving system Analog : Upper Heterodyne Digital : COFDM 4 Scart Jack (1EA) PAL, SECAM 5 Component Input (1EA) Y/Cb/Cr, Y/ Pb/Pr Remark EU (PAL Market) 6 RGB Input (1EA) RGB-PC 7 RS232C (1EA) SVC 8 HDMI Input (2 or 3EA) HDMI-PC HDMI-DTV HDMI1/DVI, HDMI2, HDMI3 9 Audio Input (2EA) RGB/DVI Audio, Component L/R Input 10 SPDIF Out (1 EA) SPDIF Out 11 USB (1EA) for SVC, S/W Download, DivX 12 LAN only DVB-T2 models 13 PCMCI (1EA) DVB-T/C Decryption Interface, CI+ Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine Analog (D-Sub 15Pin) -5- LGE Internal Use Only ADJUSTMENT INSTRUCTION 1. Application Range This spec. sheet applies to PA21A chassis applied PDP TV all models manufactured in TV factory. 3. Main PCB check process * APC - After Manual-Insult, executing APC * Boot file Download 2. Designation (1) T he adjustment is according to the order which is designated and which must be followed, according to the plan which can be changed only on agreeing. (2) Power adjustment : Free Voltage. (3) Magnetic Field Condition: Nil. (4) Input signal Unit: Product Specification Standard. (5) Reserve after operation: Above 5 Minutes (Heat Run) Temperature : at 25 °C ± 5 °C Relative humidity : 65 % ± 10 % Input voltage : 220V, 60Hz (6) A djustment equipments : Color Analyzer (CA-210 or CA-110), DDC Adjustment Jig equipment, SVC remote controller. (7) The receiver must be operated for about 5 minutes prior to the adjustment when module is in the circumstance of over 15 - In case of keeping module is in the circumstance of 0°C, it should be placed in the circumstance of above 15°C for 2 hours. - In case of keeping module is in the circumstance of below -20°C, it should be placed in the circumstance of above 15°C for 3 hours. ■ After RGB Full White in HEAT-RUN Mode, the receiver must be operated prior to the adjustment. ■ Enter into HEAT-RUN MODE 1) Press the POWER ON KEY on R/C for adjustment. 2) OSD display and screen display PATTERN MODE. ● Set is activated HEAT run without signal generator in this mode. ● Single color pattern ( WHITE ) of HEAT RUN MODE uses to check panel. ● Caution : If you turn on a still screen more than 20 minutes (Especially digital pattern, cross hatch pattern), an after image may be occur in the black level part of the screen. (8) Push The “IN STOP KEY” – For memory initialization. Case1 : Software version up 1) After downloading S/W by USB , Multi-vision set will reboot automatically 2) Push “In-stop” key 3) Push “Power on” key 4) Function inspection 5) After function inspection, Push “In-stop” key. (1) Execute ISP program “Mstar ISP Utility” and then click “Config” tab. (2) Set as below, and then click “Auto Detect” and check “OK” message If “Error” is displayed, Check connection between computer, jig, and set. (3) Click “Read” tab, and then load download file (XXXX.bin) by clicking “Read” (4) Click “Connect” tab. If “Can’t ” is displayed, Check connection between computer, jig, and set. (5) Click “Auto” tab and set as below. (6) Click "Run". (7) After downloading, check "OK" message. Case2 : Function check at the assembly line 1) When TV set is entering on the assembly line, Push “Instop” key at first. 2) Push “Power on” key for turning it on. -> If you push “Power on” key, TV set will recover channel information by itself. 3) After function inspection, Push “In-stop” key. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine -6- LGE Internal Use Only * USB DOWNLOAD(*.epk file download) (1) Put the USB Stick to the USB socket (2) Automatically detecting update file in USB Stick - If your downloaded program version in USB Stick is Low, it didn’t work. - B ut your downloaded version is High, USB data is automatically detecting (3) Show the message “Copying files from memory” * Caution : Using ‘power on’ button of the Adjustment R/C , power on Multi-vision. * ADC Calibration Protocol (RS232) (4) Updating is staring. NO Enter Adjust MODE ADC adjust Item Adjust ‘Mode In’ ADC Adjust CMD 1 A A CMD 2 A D Data 0 0 0 1 0 When transfer the ‘Mode In’, Carry the command. (5) U pdating Completed, The Multi-vision will restart automatically. (6) I f your Multi-vision is turned on, check your updated version and Tool option. (explain the Tool option, next stage) * After downloading, have to adjust TOOL OPTION again. 1) Push "IN-START" key in service remote controller. 2) Select "Tool Option 1" and Push “OK” button. 3) P unch in the number. (Each of models has their number.) 4) Completed selecting Tool option. 50PA6500-T* 60PA6500-T* Tool option 1 37056 49344 Tool option 2 39306 39306 Tool option 3 3697 3697 Tool option 4 54342 54342 Tool option 5 10 10 Automatically adjustment (The use of a internal pattern) - Adjust Sequence ▪aa 00 00 [Enter Adjust Mode] ▪xb 00 40 [Component1 Input (480i)] ▪ad 00 10 [Adjust 480i Comp1] ▪xb 00 60 [RGB Input (1024*768)] ▪ad 00 10 [Adjust 1024*768 RGB] ▪aa 00 90 End Adjust mode * Required equipment : Adjustment R/C. 3.2. Function Check 3.2.1. Check display and sound ■ Check Input and Signal items. (cf. work instructions) 1) COMPONENT (480i) 2) RGB (PC : 1024 x 768 @ 60hz) 3) HDMI 4) DVI 5) PC Audio In * Display and Sound check is executed by Remote controller. * Caution : Not to push the INSTOP KEY after completion if the function inspection. 3.1. ADC Process 3.1.1. ADC ■ Enter Service Mode by pushing “ADJ” key, ■ Enter Internal ADC mode by pushing “►” key at “5. ADC Calibration” Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine -7- LGE Internal Use Only 4. Total Assembly line process * Auto-control interface and directions 1) Adjust in the place where the influx of light like floodlight around is blocked. (Illumination is less than 100Lux). 2) Adhere closely the Color Analyzer ( CA210 ) to the module less than 10cm distance, keep it with the surface of the Module and Color Analyzer’s Prove vertically. (80~100°). 3) Aging time - After aging start, keep the power on (no suspension of power supply) and heat-run over 5 minutes. - Using ‘no signal’ or ‘full white pattern’ or the others, check the back light on. 4.1. POWER PCB Assy voltage adjustment (Vs voltage adjustment) ● Required Equipment for adjustment - D.M.M ● Condition for adjustment - No signal with the snow noise in RF mode 4.2. Adjustment Preparation ● Required Equipment - Remote controller for adjustment - Color Analyzer ( CS-1000, CA-100,100+,CA-210 or same product : CH 11 (PDP) * Please adjust CA-210, CA-100+ by CS-1000 before measuring - Auto W/B adjustment instrument(only for Auto adjustment) - 9 Pin D-Sub Jack(RS232C) is connected to the AUTO W/B EQUIPMENT. ■ Auto adjustment Map(RS-232C) RS-232C COMMAND [ CMD ID DATA ] Wb 00 00 White Balance Start Wb 00 ff White Balance End RS-232C COMMAND [CMD ID DATA] Before Adjust of White Balance, Please press POWER ONLY key - Adjust Process will start by execute RS232C Command. ● Color temperature standards according to CSM and Module CSM PLASMA Cool 11000K Medium 9300K Warm 6500K Color Coordination x Temp ± Color Coordination y COOL 0.276 0.283 11000K 0.002 MEDIUM 0.285 0.293 9300K 0.002 WARM 0.313 0.329 6500K 0.002 Downloaded from www.Manualslib.com manuals search engine Cool Mid Warm R Gain jg Ja jd G Gain jh Jb je 00 172 192 192 192 B Gain ji Jc jf 00 192 192 172 192 00 Cool Mid Warm 172 192 192 M A X 192 R Cut 64 64 64 128 G Cut 64 64 64 128 B Cut 64 64 64 128 * Manual W/B process using adjusts Remote control. ■ After enter Service Mode by pushing “ADJ” key, ■ Enter White Balance by pushing “►” key at “6. White Balance”. ■ Stick the sensor to the center of the screen and select each items(Red/Green/Blue Gain) using ▲/▼(CH +/-) key on R/C. ■ Adjust R/G/B Gain using◄/►(VOL +/-) key on R/C. ■ Adjust three modes all(Cool/Medium/Warm) : Fix the one of R/G/B Gain and Change the others. ■ When the adjustment is completed, Enter “COPY ALL”. ■ Exit adjustment mode using EXIT key on R/C. *C onnecting picture of the measuring instrument (On Automatic control) - Inside PATTERN is used when W/B is controlled. Connect to auto controller or push Adjustment R/C POWERON -> Enter the mode of White-Balance, the pattern will come out. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes CENTER (DEFAULT) * Caution - Color Temperature : COOL, Medium, Warm. - One of R Gain/G Gain/ B Gain should be kept on 0xC0, and adjust other two lower than C0. (when R/G/B Gain are all C0, it is the FULL Dynamic Range of Module) ● CS-1000/CA-100+/CA-210(CH 10) White balance adjustment coordinates and color temperature. CSM M I N -8- LGE Internal Use Only * After You finish all adjustments, Press “In-start” button and compare Tool option and Area option value with its BOM, if it is correctly same then unplug the AC cable. If it is not same, then correct it same with BOM and unplug AC cable. For correct it to the model’s module from factory JIG model. * Push The “IN STOP KEY” after completing the function inspection. And Mechanical Power Switch must be set “ON” * To check the coordinates of White Balance, you have to measure at the below conditions. - Picture mode : Vivid, Energy Saving : Off, Below the Advanced control, Dynamic Contrast : Off, Dynamic Colour : Off Colour Temp. Cool 30 Medium 0 Warm 30 * Caution : Never connect HDMI & D-sub Cable when EDID downloaded. ■ Edid data and Model option download (RS232) - Manual Download -> Picture Mode change : Vivid -> Vivid(User) 4.3. DDC EDID Write (RGB 128Byte) -> Not used any more, Use Auto D/L ■ Connect D-sub Signal Cable to D-Sub Jack. ■ Write EDID DATA to EEPROM (24C02) by using DDC2B protocol. ■ Check whether written EDID data is correct or not. * For SVC main Ass’y, EDID have to be downloaded to Insert Process in advance. 4.4. DDC EDID Write (HDMI 256Byte) -> Not used any more, Use Auto D/L NO Enter download MODE EDID data Model option download Item download ‘Mode In’ download CMD 1 A A CMD 2 A E Data 0 0 00 0 10 When transfer the ‘Mode In’, Carry the command. Automatically download (The use of a internal pattern) * Caution ● Use the proper signal cable for EDID Download - Analog EDID : Pin3 exists - Digital EDID : Pin3 exists ■ Connect HDMI Signal Cable to HDMI Jack. ■ Write EDID DATA to EEPROM(24C02) by using DDC2B protocol. ■ Check whether written EDID data is correct or not. * For SVC main Ass’y, EDID have to be downloaded to Insert Process in advance. * Caution - Never connect HDMI & D-sub Cable at the same time. - Use the proper cables below for EDID Writing. - Download HDMI1, HDMI2 separately because HDMI1 is different from HDMI2. 4.5. EDID DATA (1) All Data : HEXA Value (2) Changeable Data : * : Serial No : Controlled / Data:01 ** : Month : Controlled / Data:00 *** : Year : Controlled **** : Check sum For Analog EDID For HDMI EDID D-sub to D-sub DVI-D to HDMI or HDMI to HDMI 4.6. EDID DATA Auto Download (1) Press Adj. key on the Adj. R/C, (2) Select EDID D/L menu. (3) By pressing Enter key, EDID download will begin (4) If Download is successful, OK is display, but If Download is failure, NG is displayed. (5) If Download is failure, Re-try downloads. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine -9- No. Item Condition Hex Data 1 Manufacturer ID GSM 1E6D 2 Version Digital : 1 01 3 Revision Digital : 3 03 LGE Internal Use Only * 2D HD EDID data - 2D FHD RGB EDID data [C/S : 7C] - 2D FHD HDMI3 EDID data [C/S : 63, 56] - 2D FHD HDMI1 EDID data [C/S : 63, 76] * Vender ID Input HEX HDMI1 10 HDMI2 20 HDMI3 30 * Checksum: Changeable by total EDID data. EDID C/S data check sum (Hex) - 2D FHD HDMI2 EDID data [C/S : 63, 66] 2D-FHD HDMI RGB Block 0 0x63 0x7C Block 1 0x76(HDMI1) 0x66(HDMI2) 0x56(HDMI3) EDID C/S data check sum (Hex) Block 0 Block 1 2D-HD HDMI RGB 0x3F 0x58 0xFC(HDMI1) 0xEC(HDMI2) 0xDC(HDMI3) 4.7. Checking the EYE-Q Operation. (1) Press the EYE Key on the adjustment remote controller. (2) Check the Sensor DATA ( It must be under 10) and keep the data longer than 1.5s (3) Check ‘OK’ Green Eye-Check(Factory Mode) Sensor Data 9 Power saving mode 1 OK (Sensor DATA 0 ~ 4095, Power Saving Mode 0 ~ 12) * IF you press IN-STAP Button, change Green Eye-check OSD. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine - 10 - LGE Internal Use Only 5. Model name & Serial number Download 1) Press the ‘instart’ key of ADJ remote controller. 2) Go to the menu ‘5.Model Number D/L’ like below photo. 3) Input the Factory model name or Serial number like photo. 5.1. Model name & Serial number D/L ■ Press “Power on” key of service remocon.(Baud rate : 115200 bps) ■ Connect RS232 Signal Cable to RS-232 Jack. ■ Write Serial number by use RS-232. ■ Must check the serial number at signal test of customer support. (Refer to below). 4) Check the model name Instart menu -> Factory name displayed. 5) Check the Diagnostics (DTV country only) -> Buyer model displayed 5.2. Signal TABLE CMD LENGTH ADH ADL DATA_1 ... Data_n CS DELAY CMD: A0h LENGTH : 85~94h (1~16 bytes) ADH : EEPROM Sub Address high (00~1F) ADL : EEPROM Sub Address low (00~FF) Data : Write data CS : CMD + LENGTH + ADH + ADL + Data_1 + … + Data_n Delay : 20ms 5.3. Command Set * Description No. 1 Adjust mode EEPROM WRITE CMD(hex) A0h LENGTH(hex) 84h+n Description n-bytes Write (n = 1~16) 6. Download CI+ Key (EU model only) * Connect TV SET and PC which download keys Writing program by RS232C-Cable (1) Start “CIKeyl.exe”Program and Click (3) Button to connect TV and PC. (2) Click (5) to download CI+ Key. 43 When download succeed, you can see “OK” on (6) FOS Default write : <7mode data> write Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart, 0, Phase Data write : Model Name and Serial Number write in EEPROM,. 5.4. Method & Notice (1) Serial number D/L is using of scan equipment. (2) Setting of scan equipment operated by Manufacturing Technology Group. (3) Serial number D/L must be conformed when it is produced in production line, because serial number D/L is mandatory by D-book 4.0 * Manual Download (Model Name and Serial Number) If the TV set is downloaded By OTA or Service man, Sometimes model name or serial number is initialized.( Not always) There is impossible to download by bar code scan, so It need Manual download. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine - 11 - LGE Internal Use Only (3) result value - normally status for download : OKx - abnormally status for download : NGx ■ Check the method of RS232C Command (1) into the main ass’y mode (RS232 : aa 00 00) CMD1 CMD2 A A Data 0 0 0 (2) c heck the key download for transmitted command (RS232 : ci 00 10) CMD1 CMD2 C 1 8. SW Download Guide. Data 0 1 (1) Put the USB Stick to the USB socket (2) Automatically detecting update file in USB Stick * If your downloaded program version in USB Stick is Low, it didn’t work. B ut your downloaded version is High, USB data is automatically detecting. (3) Show the message “Copying files from memory” (4) Updating is staring. (5) Updating Completed, The TV will restart automatically. After turn on TV, Please press ‘IN-STOP’ button on ADJ Remote-control. * IF you don’t have ADJ R/C, enter ‘Factory Reset’ in OPTION MENU. (6) When TV turn on, check the Updated version on Diagnostics MENU. 0 (3) result value - normally status for download : OKx - abnormally status for download : NGx ■ Check the method of CI+ Key value (RS232) (1) into the main ass’y mode (RS232 : aa 00 00) CMD1 CMD2 A A Data 0 0 0 (2) check the mothed of CI+ key by command (RS232 : ci 00 20) CMD1 CMD2 C 1 * Put a *.bin to USB Stick and Turn on TV Data 0 1 0 (3) result value i 01 OK 1d1852d21c1ed5dcx └──> CI+ Key Value 7. Download MAC Address, CI+ Key and widevine Key. - Check whether the key was downloaded or not at ‘In Start’ menu. (Refer to below). -> MAC Address need only DVB-T2 Model (ex.50PA650T-ZA). * C onnect TV SET and PC which download keys Writing program by RS232C-Cable 1) Start “MAC+CIKeyl.exe”Program and Click (3) Button to connect TV and PC. 2) Click (4) to download MAC Address. 3) Click (5) to download CI+ Key. 4) When download succeed, you can see “OK” on (6) * Each Chassis has it’s own MAC Address. Please be careful of download. ■ Check the method of RS232C Command (1) into the main ass’y mode (RS232 : aa 00 00) CMD1 CMD2 A A Data 0 0 0 (2) c heck the key download for transmitted command (RS232 : ci 00 10) CMD1 CMD2 C 1 Data 0 1 0 Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine - 12 - LGE Internal Use Only BLOCK DIAGRAM Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine - 13 - LGE Internal Use Only EXPLODED VIEW IMPORTANT SAFETY NOTICE 601 A12 520 A9 501 A2 910 400 900 120 240 590 LV1 A10 206 203 202 207 204 200 205 302 201 580 301 208 305 209 304 303 540 300 310 Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine - 14 - LGE Internal Use Only +5V Full SCART PDP GP4 LM1 EAX64280504 MULTI E L103 120-ohm EU +3.3V MMBT3906(NXP) Q103-*1 EU JK100 PSC008-02 C R104 10K EU AV/SC1_DET R129 0 EU B SC1_SOG_IN C C 23 B AV/SC1_CVBS_IN AV_DET C109 27pF 50V EU R117 75 EU 22 COM_GND 21 SYNC_IN C111 220pF 50V EU 20 Q100 MMBT3904(NXP) EU E SYNC_GND1 5% 1/16W R113 75 EU SYNC_GND2 18 17 B R134 100 1/4W EU R141 220 EU R135 0 EU SC1_FB R_OUT RGB_GND R106 75 14 R_GND R123 33 EU R119 75 EU SC1_R+/COMP1_Pr+ 15 R114 10K EU D2B_OUT 12 G_OUT R108 75 D2B_IN 10 A1 ID R115 470K EU C102 R121 1000pF 10K 50V EU READY R126 12K EU R116 470K EU C103 R124 1000pF 10K EU 50V READY R127 12K EU EU C 12K R160 E EU 1K R158 SC_RE1 B E EU MMBT3904(NXP) B Q105 C EU MMBT3904(NXP) B Q107 MULTI D112-*1 MMBD6100 A2 AV/SC1_L_IN G_GND 9 C R120 2.7K EU SC1_G+/COMP1_Y+ 11 E EU MMBT3904(NXP) Q106 EU KDS184 D112 A2 REC_8 SC1_ID 13 DTV/MNT_VOUT C116 10uF 16V EU R147 10K EU R143 180 EU R142 390 READY RGB_IO 16 C E Q104 MMBT3904(NXP) EU C110 1000pF 50V READY C106 100uF 16V EU R118 470K EU R146 18K EU Q103 ISA1530AC1 EU R136 330 EU SC1_VOUT SYNC_OUT 19 C117 0.1uF 16V READY R144 470 EU E R105 1K EU SHIELD B EU 12K R159 C C EU R155 3K A1 SC1_B+/COMP1_Pb+ 7 AUDIO_L_IN 6 R107 75 B_GND SC_RE2 EU 7.5K R156 8 B_OUT EU 1K R157 AV/SC1_R_IN 5 P_17V IC101 AZ4580MTR-E1 P_17V AUDIO_GND 4 AUDIO_L_OUT R138 2K EU Q101 MMBT3904(NXP) EU C114 27pF 50V EU C113 10uF 16V EU R149 15K EU R145 6.8K EU R137 2K EU R139 2K EU Q102 MMBT3904(NXP) EU C112 10uF 16V EU +3.3V_ST R154 5.6K EU 3 6 IN2- VEE 4 5 IN2+ EU 5.6K R153 SCART1_Rout SCART1_MUTE EU 33 AR105 /PCM_OE /PCM_WE CI_IORD /PCM_IORD /PCM_IOWR AR106 EU 33 CI_ADDR[12] C101 0.1uF 16V EU OUT2 IN1+ EU R189 10K CI_IOWR PCM_A[12] PCM_A[13] CI_ADDR[13] CI_ADDR[14] PCM_A[14] /PCM_REG REG BUF2_FE_TS_DATA[0-7] BUF2_FE_TS_DATA[0] +5V EU /CI_CD1 R102 100 EU 3 4 PCM_D[5] 39 5 PCM_D[6] CI_TS_DATA[6] CI_TS_DATA[7] 40 6 41 7 42 8 PCM_D[7] R130 33 EU 1/16W R1315% 33 EU 37 33 R111 10K EU CI_IORD CI_IOWR BUF2_FE_TS_DATA[0-7] PCM_D[3] 38 EU BUF2_FE_TS_SYN BUF2_FE_TS_DATA[0-7] EU 36 CI_TS_DATA[5] AR100 BUF2_FE_TS_DATA[2] READY R112 0 BUF2_FE_TS_DATA[3] CI_ADDR[10] CI_ADDR[11] 11 CI_ADDR[9] 12 CI_ADDR[8] 15 16 51 17 18 53 BUF2_FE_TS_DATA[4] BUF2_FE_TS_DATA[5] R109 10K EU BUF2_FE_TS_DATA[6] BUF2_FE_TS_DATA[7] PCM_RST /PCM_WAIT R100 EU 33 R101 EU 33 REG CI_TS_CLK AR101 33 EU AR102 33 EU CI_TS_VAL CI_TS_SYNC R110 0 READY 19 54 20 55 1A3 CI_ADDR[5] READY BUF2_FE_TS_VAL_ERR BUF2_FE_TS_CLK CI_ADDR[12] 22 CI_ADDR[7] CI_ADDR[6] 24 CI_ADDR[5] 59 25 CI_ADDR[4] 60 26 CI_ADDR[3] CI_ADDR[2] 29 2Y3 2Y2 23 27 1A2 PCM_A[1] CI_ADDR[6] PCM_A[2] 21 28 2Y4 /PCM_IRQA 58 63 1A1 CI_ADDR[7] 100 EU 56 61 IC100 TC74LCX244FT 1OE CI_DET PCM_A[0] 0 57 62 EU R165 10K CI_OE CI_WE R132 R128 AR104 33 AR108 33 EU BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3] AR109 33 EU BUF2_FE_TS_DATA[4] BUF1_FE_TS_DATA[4] BUF2_FE_TS_DATA[5] BUF1_FE_TS_DATA[5] BUF2_FE_TS_DATA[6] BUF1_FE_TS_DATA[6] BUF2_FE_TS_DATA[7] BUF1_FE_TS_DATA[7] 1A4 PCM_A[3] 2Y1 CI_ADDR[4] GND 1 EU 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 EU C105 0.1uF 16V VCC AR110 33 BUF1_FE_TS_SYN EU BUF2_FE_TS_SYN BUF2_FE_TS_VAL_ERR BUF1_FE_TS_VAL_ERR 2OE BUF1_FE_TS_CLK BUF2_FE_TS_CLK 1Y1 CI_ADDR[0] 2A4 PCM_A[7] 1Y2 CI_ADDR[1] 2A3 PCM_A[6] 1Y3 CI_ADDR[2] 2A2 PCM_A[5] 1Y4 CI_ADDR[3] 2A1 PCM_A[4] CI POWER ENABLE CONTROL +5V +5V_CI_ON S R184 10K READY CI_ADDR[1] EU CI_ADDR[0] R187 10K EU 30 31 PCM_D[1] 66 32 PCM_D[2] CI_TS_DATA[1] 67 33 CI_TS_DATA[2] 68 34 R150 10K EU 2 G2 69 R103 100 EU CI_ADDR[0-14] C131 0.1uF 16V READY G C104 0.1uF 16V EU R198 10K READY 3.3V_CI C PCM_D[0-7] THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Downloaded from www.Manualslib.com manuals search engine PCM_5V_CTL PCM_D[0-7] +3.3V R188 2K EU G1 1 /CI_CD2 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes L100 120-ohm EU AO3407A CI_TS_DATA[3] +5V Q114 RSR025P03 EU D PCM_D[0] 64 65 CI_TS_DATA[0] PCM_A[11] +3.3V_CI CI_ADDR[14] 14 50 52 CI_ADDR[11] +3.3V_CI CI_ADDR[13] 13 49 BUF2_FE_TS_DATA[3] BUF1_FE_TS_DATA[0-7] 9 10 46 48 BUF2_FE_TS_DATA[1] BUF2_FE_TS_DATA[2] PCM_A[9] PCM_A[10] /PCM_CE 44 47 BUF2_FE_TS_DATA[0] PCM_A[8] CI_ADDR[10] R133 10K EU 45 43 33 CI_ADDR[9] AR103 33 PCM_D[4] CI_TS_DATA[4] BUF2_FE_TS_DATA[1] AR107 CI_ADDR[8] S R151 10K EU JK102 10067972-000LF EU 35 B R181 10K EU D C100 22uF 10V EU VCC 7 R152 6.8K EU R148 15K EU CI_WE +5V_CI_ON 8 2 R140 2K EU CI_OE CI SLOT 1 IN1- SCART1_Lout C115 27pF 50V EU DTV_R_OUT OUT1 +3.3V_CI G AUDIO_R_OUT 1 5% 1/16W AUDIO_R_IN 2 BUF1_FE_TS_DATA[0-7] C107 5600pF 50V EU C108 5600pF 50V EU 3 MULTI Q114-*1 L101 120-ohm EU Q113 MMBT3904(NXP) EU C136 0.1uF 16V READY E GP4_S7LR SCART,CI Slot C137 0.1uF 16V EU 2011-10-20 1 6 LGE Internal Use Only SPDIF SIDE_HDMI_2 +5V 16 DATA0+ DATA0CLK+ CLK_SHIELD CLKCEC NC SCL DDC_SDA_1 SDA DDC/CEC_GND +5V_POWER 15 JP202 R208 33 HDMI_1 14 13 12 9 8 7 6 4 3 2 19 8 18 9 10 11 13 14 15 R237 10K SIDE_HDMI_1 Q202 R241 1.8K SIDE_HDMI_2MMBT3904(NXP) SIDE_HDMI_2 19 R250 10K SIDE_HDMI_2 E R244 3.3K R289 SIDE_HDMI_2 R245 10K SIDE_HDMI_233 SIDE_HDMI_2 DDC_SDA_3 18 DDC_SDA_2 R288 10K SIDE_HDMI_2 16 R260 56K READY 17 DDC_SCL_2 18 15 19 20 SHIELD 14 13 CK-_HDMI1 12 11 10 9 D0-_HDMI1 8 D0_GND 7 D0+ D0+_HDMI1 6 D1D1-_HDMI1 5 D1_GND 4 D1+ D1+_HDMI1 3 D2D2-_HDMI1 D2_GND 2 D2+ 1 R232 33 SIDE_HDMI_1 15 CK-_HDMI2 13 11 10 D0-_HDMI2 9 D0D0_GND 8 D0+ D0+_HDMI2 D1D1-_HDMI2 D1_GND 7 6 5 D1+ D1+_HDMI2 D2D2-_HDMI2 D2_GND 4 3 2 D2+ D2+_HDMI2 D2+_HDMI1 CEC_REMOTE 1 C219 0.1uF 16V 1 VINPUT R285 100 SPDIF_OUT S B GND 2 VCC 3 VIN CEC_REMOTE_S7 PEN_TOUCH +5V_ST D225 B140A D SIDE USB D222 READY CK+ 1 4 C220 10pF 50V FIX_POLE D224 MMBD301LT1G 30V READY R268 100 CEC_REMOTE CK-_HDMI3 12 CK+_HDMI2 CK+ R269 27K READY R261 0 READY DDC_SCL_3 R246 33 SIDE_HDMI_2 14 CEC_REMOTE VCC 2 R209 10K SIDE_HDMI_2 HPD3 B 17 16 16 HDMI_ARC CEC_REMOTE CK+_HDMI1 D0- R286 10K SIDE_HDMI_1 17 12 Q201 MMBT3904(NXP) SIDE_HDMI_1 E R230 3.3K R231 R287 SIDE_HDMI_1 33 10K SIDE_HDMI_1 SIDE_HDMI_1 R227 1.8K SIDE_HDMI_1 7 +3.3V_ST C 1A SPEC IC207 2 +3.3V VOUT SWITCH ADDED +3.3V +5V +5V_ST IC204 AP2191SG-13 1 40V READY D0- AP2337SA-7 PEN_TOUCH VIN 3 Q203 BSS83 CK+_HDMI3 GND D0-_HDMI3 R264 Capacitors on VBUSA should be 10K placed as closd to connector as possible. D0_GND G NC D0+ OUT_2 JK209 3AU04S-305-ZC-(LG) D0+_HDMI3 D1D1-_HDMI3 D1_GND D1+ D1+_HDMI3 D2D2-_HDMI3 D2_GND D2+ D2+_HDMI3 8 1 7 2 GND R270 10K R243 0 R247 0 READY IN_1 $0.11 OUT_1 C213 10uF 10V USB1_OCD C212 0.1uF 16V SIDE_USB_DM SIDE_USB_DP R258 33 FLG 6 3 5 4 IN_2 EN USB1_CTL R271 33 5 1 5 6 20 USB DOWN STREAM 5 CK+ R203 10K SIDE_HDMI_1 HPD2 B 4 11 10 HPD DDC_SCL_1 C SHIELD DATA1- DATA0_SHIELD R226 1K SIDE_HDMI_1 4 Fiber Optic HPD1 R217 10K HDMI_1 20 2 3 +5V 4 DATA1+ GND 1 R281 10K HDMI_1 17 Q200 MMBT3904(NXP) HDMI_1 E R204 3.3K R207 R282 HDMI_133 10K HDMI_1 HDMI_1 JP201 R201 1.8K HDMI_1 18 DATA2- DATA1_SHIELD JP208 B 19 DATA2_SHIELD R240 5V_DET_HDMI_3 1K SIDE_HDMI_2 JP207 YKF45-7058V HDMI1_NON Screw DATA2+ 1 R202 10K HDMI_1 C JP204 5V_DET_HDMI_1 R200 1K HDMI_1 JP205 SHIELD 20 BODY_SHIELD 5V_DET_HDMI_2 Fiber Optic For CEC BODY_SHIELD JK200-*1 MULTI JK204-*1 2F01TC1-CLM97-4F JK204 JST1223-001 5V_HDMI_3 +5V 3 5V_HDMI_2 +5V 2 5V_HDMI_1 3 SIDE_HDMI_1 HDMI_1 JK211 PPJ239-01 5H COMPONENT2 RS232C R283 R284 JK203 SPG09-DB-009 [RD1]O-SPRING_2 [GN]E-LUG 6A [RD1]CONTACT_2 +3.3V R251 75 [GN]O-SPRING [WH1]O-SPRING R259 10K R276 100 R266 1K R252 75 +5V_ST [RD]O-SPRING_1 [RD1]O-SPRING_1 5 COMP2_Pr+ 5C 10 Q204 MMBT3904(NXP) USA [RD]CONTACT_1 [RD1]E-LUG-S 5E [BL1]O-SPRING 7E [BL1]E-LUG-S 4D [GN1]CONTACT 5D [GN1]O-SPRING 6D [GN1]E-LUG 4N [RD]CONTACT_2 5E [RD]O-SPRING_2 6E [RD]E-LUG R235 470K R236 12K 5L [RD2]O-SPRING_1 R238 470K R242 12K 11 7 12 9 V_SYNC 4 14 [RD2]E-LUG-S [BL2]O-SPRING 7K [BL2]E-LUG-S GND_1 SYNC_GND 15 C1- C228 0.1uF 16V R296 10K READY 2 4 C2+ C2- 11 6 ET_NET 5 C226 0.1uF 16V DIN2 10 7 9 8 TP BS-R430051 2 1 3 3 TN 4 4 RP 5 5 6 7 6 1 ET_NET_UDE 2 3 4 5 6 7 6 RN C200 0.1uF 16V ET_NET 7 V8 ROUT2 JK210-*1 1 2 3 C225 0.1uF 16V 8 8 9 D200 D204 5.6V 5.6V ET_NET ET_NET D205 5.6V ET_NET D206 5.6V ET_NET 9 8 DOUT2 9 9 RIN2 C227 0.1uF 16V USA C202 10pF 50V 6A 7A B_TERMINAL1 RGB_DDC_SDA DSUB_G+ R216 75 DSUB_HSYNC +3.3V R273 0 ET_NET R291 0 ET_NET R280 0 ET_NET R290 0 ET_NET R_SPRING 5 T_SPRING C203 10pF 50V DSUB_VSYNC R224 10K R225 1K 7B B_TERMINAL2 6B T_TERMINAL2 R218 470K R222 12K E_SPRING T_TERMINAL1 7A B_TERMINAL1 IR 4 R_SPRING 5 T_SPRING R220 10K PC_R_IN 4 DSUB_B+ 3 6A E_SPRING T_TERMINAL1 DSUB_R+ R206 33 DDC_CLOCK 5 V+ 1 JK207 PEJ027-04 R215 75 R205 33 BLUE NC 10 5K DIN1 5 JK206 PEJ027-04 R214 75 GREEN H_SYNC 13 7B B_TERMINAL2 6B T_TERMINAL2 R213 0 NON_USA TX R221 10K R210 10 USA PC_L_IN R219 470K R223 12K DSUB_DET RGB_DDC_SCL PC_SER_DATA DDC_GND R212 10 SC1_R+/COMP1_Pr+ 7L R233 100K USA 12 +2.5V JK210 XRJV-01V-0-D12-080 C1+ 7 R274 0 NON_RGB 3 RED BLUE_GND 8 3 COMP1_L_IN 4 R263 12K R298 10K DDC_DATA 2 NON_EU [WH2]O-SPRING NON_EU 5M R255 470K 13 3 COMP2_R_IN GREEN_GND COMP1_R_IN ROUT1 PC_SER_DATA R275 0 NON_RGB PC_SER_CLK R262 12K R257 10K GND_2 1 NON_EU R239 10K 2 RED_GND 6 [RD2]O-SPRING_2 15 +5V_ST [RD2]E-LUG [RD2]CONTACT R254 470K R297 10K NON_EU R234 10K 1 PC AUDIO JK205 SPG09-DB-010 NON_EU 5N [WH]O-SPRING 4E RGB PC NON_EU 6N COMP2_L_IN R256 10K 5D R229 100K USA B E 4C 7F 16 14 RIN1 TX C 9 R253 75 7C C229 0.1uF 16V 4 R267 1K [RD]E-LUG-S DOUT1 R228 10K USA 8 AV2_DET 5B R277 100 3 COMP2_Pb+ [RD1]CONTACT_1 GND 2 COMP2_DET R265 10K [BL]O-SPRING 5F VCC 4A 7B +3.3V_ST IC206 MAX3232CDR 1 7 [BL]E-LUG-S ETHERNET S7_TXD S7_RXD PM_TXD PM_RXD 0 0 R279 10K 6 COMP2_Y+ [GN]CONTACT 4F R278 10K JK208 PPJ234-02 5A 5G +3.3V_ST [RD1]E-LUG EU 4H 10mm 1/16W 5% NON_EU 6H JK202 SIDE_HDMI_2 1/16W 5% JK201 SIDE_HDMI_1 JK200 HDMI_1 16 R211 10 PC_SER_CLK SHILED SC1_B+/COMP1_Pb+ GND +3.3V 4J [GN2]CONTACT 5J [GN2]O-SPRING 6J [GN2]E-LUG NON_EU R248 10K NON_EU R249 1K COMP1_DET SC1_G+/COMP1_Y+ THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine GP4_S7LR JACK INTERFACE 2011-10-20 2 6 LGE Internal Use Only TUNER BUF1_FE_TS_DATA[0-7] FE_TS_DATA[1] AR300 FNIM 33 BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] FE_TS_DATA[2] BUF1_FE_TS_DATA[2] FE_TS_DATA[3] BUF1_FE_TS_DATA[3] FE_TS_DATA[0] AR301 FNIM 33 BUF1_FE_TS_DATA[4] FE_TS_DATA[4] FE_TS_DATA[5] TUNER OPT1 BUF1_FE_TS_DATA[5] BUF1_FE_TS_DATA[6] FE_TS_DATA[6] FE_TS_DATA[7] OPT3 X TDSS-G101D DVB-T/C OPT2 HNIM TDSS-H101F ATSC HNIM TDSH-T101F DVB-T_SCA HNIM RF_SW TDSN_B001F SBTVD FNIM RF_SW TDSN_G201D DVB_T2 FNIM BUF1_FE_TS_DATA[7] AR302 33 FE_TS_DATA[0-7] FNIM BUF1_FE_TS_SYN FE_TS_SYN X FE_TS_VAL_ERR BUF1_FE_TS_VAL_ERR BUF1_FE_TS_CLK FE_TS_CLK X RF_SWITCH R310 1K RF_SWITCH_CTL C307 0.1uF 16V RF_SWITCH Close to Tuner Pin TU303 TDSN_B001F TU304 TDSN-G301D 1 2 3 4 5 6 7 8 9 10 11 +1.25V_TU 12 13 C300 10uF 6.3V FNIM C301 0.1uF 16V FNIM DVB_T/C SBTVD DVB_T2 14 15 16 17 18 19 20 21 22 23 24 25 26 27 NC_1 1 RESET 2 SCL 3 SDA 4 +B1[3.3V] 5 SIF 6 +B2[1.8V] 7 CVBS 8 +B3[2.5V] 9 NC_2 10 NC_3 11 +B4[3.3V] 12 +B5[1.23V] 13 NC_4 14 GND 15 ERROR 16 SYNC 17 VALID 18 MCLK 19 D0 20 D1 21 D2 22 D3 23 D4 24 D5 25 D6 26 D7 ATSC 27 RF_S/W_CTL 1 RESET 2 SCL 3 SDA 4 +B1[3.3V] 5 SIF 6 +B2[1.8V] 7 CVBS 8 NC_1 9 NC_2 10 NC_3 11 NC 2 SCL 3 SDA 4 +3.3V 5 SIF 6 +1.8V 7 CVBS 8 IF_AGC 9 DIF[P] 10 DIF[N] 11 NC 1 RESET 2 SCL 3 SDA 4 +B1[3.3V] 5 SIF 6 +B2[1.8V] 7 CVBS 8 IF_AGC 9 DIF[P] 10 DIF[N] 11 +B3[3.3V] +B4[1.23V] NC_4 SHIELD SHIELD RF_S/W_CTL RESET R308 R301 2.2K 100 SCL R307 +2.5V_TU SDA R306 22 TUNER_RESET +B1[3.3V] SIF +B2[1.8V] CVBS IF_AGC C302 0.1uF 16V C303 10uF 16V DVB_T2 0 16V 0.1uF C310 C304 68pF 50V 22 R303 R304 0 R305 TU_SDA C305 68pF 50V C311 0.1uF 16V Close to Tuner Pin R302 HNIM 0 HNIM 0 TU_SCL IF_AGC_MAIN DIF[P] DIF[N] HNIM SHIELD Close to Tuner Pin GND R311 10K R309 2.2K IF_P_MSTAR IF_N_MSTAR +5V READY 16V 0.1uF C306 12 12 12 +1.8V_TU DVB_T_SCA 1 RESET +3.3V_TU +3.3V_TU TU300 TDSH-T101F TU301 TDSS-H101F TU302 TDSS-G101D R316 470 C308 0.1uF 16V R312 4.7K ERROR R317 82 E B TU_SIF MMBT3906(NXP) Q301 C SYNC FE_TS_SYN VALID FE_TS_VAL_ERR MCLK D0 FE_TS_CLK FE_TS_DATA[0] D1 FE_TS_DATA[1] D2 FE_TS_DATA[2] D3 FE_TS_DATA[3] D4 FE_TS_DATA[4] D5 FE_TS_DATA[5] D6 FE_TS_DATA[6] D7 FE_TS_DATA[7] FE_TS_DATA[0-7] TU_CVBS 28 28 SHIELD SHIELD THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Tuner block 3 6 TUNER Copyright © 2011 LG Electronics Inc. All rights reserved. Downloaded from www.Manualslib.com manuals search engine Only for training and service purposes LGE Internal Use Only VIDEO/AUDIO IC400 LGE2111A-T8 IC400-*1 LGE2111A-TE F5 B6 E5 D5 B7 E7 F7 AB5 AB3 A9 F4 AB1 N6 AB2 AC2 LVA0P GPIO36 AB23 LVA0N GPIO37 GPIO38 LVA1P GPIO39 LVA1N AC25 AB24 AD25 LVA2P GPIO40 GPIO41 LVA2N GPIO42 LVA3P AC24 AE23 AC23 LVA3N GPIO45 GPIO46 LVA4P GPIO49 LVA4N AC22 AD23 GPIO50 GPIO51 V23 Dvix only LVB0P U24 LVB0N GPIO52 I2C_SCKM0/GPIO53 LVB1P I2C_SDAM0/GPIO54 LVB1N V25 J1 K2 K1 L2 L3 T5 T4 V5 AC4 RXACKP VIFP RXACKN VIFM RXA0P AD3 IP RXA1P AE3 C432 C433 IM RXA1N SIFP SIFM 0.1uF 0.1uF R464 R465 L400 120-ohm Main AC5 47 47 R446 DDCDA_DA/GPIO24 10K DDCDA_CK/GPIO23 PCM_A[0-14] TU_SIF V24 AD2R452 W23 LVB2N IF_AGC AA23 LVB3P AE2 RF_AGC Y24 LVB3N HNIM AA25 LVB4P AA24 LVB4N AE6 AE24 LVACKP I2C_SCKM1/GPIO75 AD24 LVACKN AD6 I2C_SDAM1/GPIO76 Y23 LVBCKP R497 0 C450 100pF 50V HNIM C435 0.1uF HNIM TU_SCL TU_SDA C1612 0.047uF 25V 100 HNIM IF_AGC_MAIN C1613 0.1uF HNIM HNIM W24 LVBCKN AE11 AD11 AE8 AD8 AC8 SPDIF_IN/GPIO152 RXCCKN SPDIF_OUT/GPIO153 RXC0N USB0_DM RXC1N USB0_DP RXC2P F3 F1 G2 G1 H2 DSUB_G+ DSUB_B+ R400 10K R403 2.4K 22 22 33 68 33 68 33 68 0 H3 R6 U6 P5 R4 USB1_DM USB1_DP RXDCKN I2S_IN_SD/GPIO151 R413 R414 R415 R416 R417 R418 33 68 33 68 33 68 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF C408 C409 C410 C411 C412 C413 C414 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF C415 C416 C417 C418 C419 C420 C421 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF N2 P3 N3 N1 M3 M2 M1 C447 5pF 5pF X400 24MHz GND_1 4 R441 1M X-TAL_1 SIDE_USB_DM SIDE_USB_DP AE12 SC1_G+/COMP1_Y+ SC1_B+/COMP1_Pb+ SC1_SOG_IN U2 T1 T2 R2 R1 T3 Y15 R473 10K I2S_OUT_MCK/GPIO154 I2S_OUT_SD/GPIO157 D9 R462 22 B9 RXD2P Y19 AB17 Y16 AB19 AB20 AA16 AA19 AC21 AA17 AD22 AD20 C10 Y21 Y18 Y22 PCM_RST /CI_CD1 /CI_CD2 C437 C438 AB9 HSYNC0 AUL1 VSYNC0 AUR1 RIN0P AUL2 RIN0M AUR2 GIN0P AUL3 GIN0M AUR3 BIN0P AUL4 BIN0M AA11 EU 2.2uF 2.2uF AV/SC1_L_IN AV/SC1_R_IN Y9 NON_EU C472 NON_EU C478 C443 C444 C445 C446 AA7 AB8 Y8 Y10 AC7 AD7 AUR4 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF COMP1_L_IN COMP1_R_IN COMP2_L_IN COMP2_R_IN PC_L_IN PC_R_IN HSYNC1 V6 EU R442 V4 100 W6 AUOUTL0 RIN1P AUOUTL2 RIN1M AUOUTL3 GIN1P AUOUTR0 GIN1M AUOUTR2 BIN1P AUOUTR3 PCMADR[2]/GPIO122 NF_WEZ/GPIO140 PCMADR[3]/GPIO121 NF_ALE/GPIO141 PCMADR[4]/GPIO99 R479 R480 22 22 E4 N24 A8 22 22 R469 R470 RGB_DDC_SDA RGB_DDC_SCL NF_RBZ/GPIO142 B6 COMP1_DET E5 AV/SC1_DET D5 AMP_RESET_N TUNER_RESET B7 E7 PCM_5V_CTL F7 AB5 AMP_SCL AMP_SDA R438 AB3 1K PCMADR[8]/GPIO108 R486 H5 PCMADR[9]/GPIO110 GPIO_PM[0]/GPIO6 PCMADR[10]/GPIO114 PM_UART_TX/GPIO_PM[1]/GPIO7 PCMADR[11]/GPIO112 GPIO_PM[2]/GPIO8 PCMADR[12]/GPIO104 GPIO_PM[3]/GPIO9 PCMADR[13]/GPIO107 GPIO_PM[4]/GPIO10 PM_UART_RX/GPIO_PM[5]/GPIO11 PM_SPI_SCZ1/GPIO_PM[6]/GPIO12 PCMREG_N/GPIO123 GPIO_PM[7]/GPIO13 PCMOE_N/GPIO113 GPIO_PM[9]/GPIO15 PCMWE_N/GPIO197 PM_SPI_SCZ2/GPIO_PM[10]/GPIO16 GPIO_PM[8]/GPIO14 PCMIORD_N/GPIO111 100 AC_DET PM_TXD DISP_EN 5V_ON RL_ON PM_RXD R449 J6 K4 L6 C2 PM_SPI_SDI/GPIO2 PM_SPI_SDO/GPIO3 N6 USB1_OCD AB2 AC2 COMP2_Y+ COMP2_Pb+ 33 68 33 68 33 68 0 W2 Y3 P24 22 22 V1 W3 TS0VALID/GPIO85 R489 33 33 R490 33 W1 N23 P22 R21 P20 F6 EU W5 SCART1_Rout U5 AE5 AUVRP TU_CVBS AV/SC1_CVBS_IN COMP2_Y+ 0.047uF 0.047uF 0.047uF Y4 W4 AA5 R444 100 G5 G4 J5 J4 C400 1000pF READY Y5 AA4 50V Y6 AA1 DTV/MNT_VOUT CVBS2 ET_RXD[0]/RP/GPIO60 ET_TXD[0]/TP/GPIO57 CVBS4 CVBS5 CVBSOUT0 R433 68 C428 0.047uF C431 4.7uF C434 1uF C449 0.1uF C454 10uF L401 BLM18SG121TN1D AC6 T21 T22 VCOM ET_TX_EN/GPIO58 ET_MDC/GPIO61 ET_MDIO/GPIO62 Y12 TS0DATA_[1]/GPIO78 TS0DATA_[2]/GPIO79 UART1_TX/GPIO43 TS0DATA_[3]/GPIO80 TS0DATA_[4]/GPIO81 UART2_TX/GPIO65 TS0DATA_[5]/GPIO82 UART2_RX/GPIO64 TS0DATA_[6]/GPIO83 UART3_TX/GPIO47 TS0DATA_[7]/GPIO84 Y11 AA12 AB12 AA14 AB14 AA13 AB11 AC15 TS1CLK/GPIO98 I2C_SCKM2/DDCR_CK/GPIO72 TS1VALID/GPI96 I2C_SDAM2/DDCR_DA/GPIO71 TS1SYNC/GPIO97 TS1DATA_[0]/GPIO88 TS1DATA_[1]/GPIO89 TS1DATA_[3]/GPIO91 TS1DATA_[4]/GPIO92 PWM1/GPIO67 TS1DATA_[5]/GPIO93 PWM2/GPIO68 AC16 TS1DATA_[6]/GPIO94 PWM3/GPIO69 TS1DATA_[7]/GPIO95 AE15 AE14 AC13 AC14 AD12 AD13 AD14 GPIO193 GPIO194 RP TP C5 POWER C4 RN ETH_LED1 D5 B7 E7 F7 AB5 AB3 A9 F4 AB1 N6 AB2 AC2 LVA0P LVA0N GPIO38 LVA1P GPIO39 LVA1N GPIO40 LVA2P GPIO41 LVA2N GPIO42 LVA3P GPIO45 LVA3N GPIO46 LVA4P GPIO49 LVA4N GPIO50 I2C_SCKM0/GPIO53 LVB0N LVB1P I2C_SDAM0/GPIO54 LVB1N GPIO73 LVB2P GPIO74 C7 E6 AC25 LVB2N LVB3P LVB3N LVB4P B6 E5 AC24 B7 E7 AC22 AD23 LVBCKP F4 AB1 V24 GPIO196 GPIO195 N6 W25 AB2 W23 AC2 C3 A3 B3 B4 TN CI_DET R402 EU 22 DSUB_DET AV2_DET ETH_LED0 PIN NAME LVA0P LVA0N SPI1_CK/GPIO201 SPI1_DI/GPIO202 SPI2_CK/GPIO203 GPIO38 LVA1P GPIO39 LVA1N GPIO40 LVA2P GPIO41 LVA2N GPIO42 LVA3P GPIO45 LVA3N GPIO46 LVA4P GPIO49 LVA4N GPIO50 R445 R443 R460 R431 49.9 49.9 49.9 49.9 1% 1% 1% 1% ET_NET ET_NET ET_NET ET_NET MODEL_OPT_1 A9 MODEL_OPT_2 C458 0.1uF ET_NET 3D F4 2D FHD HD +3.3V T6 N5 R1401 1K READY R401 1K FHD R430 1K 3D I2C_SCKM0/GPIO53 LVB0N LVB1P I2C_SDAM0/GPIO54 LVB1N GPIO73 LVB2P GPIO74 LVB2N AA23 LVB3P LVB3N AA25 AA24 AD24 Y23 W24 U23 T24 T23 HDMI_ARC ARC AC25 AB24 C1419 0.1uF AD25 MODEL_OPT_3 R1400 1K READY R1406 150 READY R419 1K HD R467 1K 2D READY AC23 AC22 AD23 R1407 63.4 READY LVB4P U24 +3.3V_ST V25 GND W23 C429 22uF 16V AA24 AD24 Y23 GPIO196 A-TMA0 A-TMA1 A-TMA2 A-TMA3 A-TMA4 A-TMA5 A-TMA6 A-TMA7 A-TMA8 A-TMA9 A-TMA10 A-TMA11 A-TMA12 A-TMA13 A-TMA14 A-TMBA0 A-TMBA1 A-TMBA2 A-TMODT A-TMRASB A-TMCASB A-TMWEB A-TMDQSL A-TMDQSLB R436 10 W24 SOC_RESET T25 GPIO193 L10 M12 M13 N12 P14 R10 R14 C1413 10uF R15 T10 C436 0.1uF A-TMDQSU A-TMDQSUB U23 T24 T23 GPIO195 R434 100K D400 KDS181 C430 0.1uF 16V A-TMDML A-TMDMU <LM1 CHIP Config> (AUD_SCK,AUD_MASTER_CLK,PWM1,PWM0) B51_NO_EJ SB51_WOS SB51_WS MIPS_SPI_NO_EJ MIPS_SPI_EJ_1 MIPS_SPI_EJ_2 MIPS_WOS MIPS_WO RXB1+ RXB0- AA24 RXB0+ RXA2- AD24 RXA2+ Y23 RXB2- W24 RXB2+ U23 T24 T23 G10 GND_32 GND_33 VDDC_1 GND_34 VDDC_2 GND_35 VDDC_3 GND_36 VDDC_4 GND_37 VDDC_5 GND_38 VDDC_6 GND_39 VDDC_7 GND_40 VDDC_8 GND_41 VDDC_9 GND_42 VDDC_10 GND_43 VDDC_11 GND_44 VDDC_12 GND_45 VDDC_13 GND_46 GND_47 A11 C14 B11 F12 C15 E12 A14 D11 B14 D12 C16 C13 A15 E11 B13 B23 A_DDR3_A[0] B_DDR3_A[0] A_DDR3_A[1] B_DDR3_A[1] A_DDR3_A[2] B_DDR3_A[2] A_DDR3_A[3] B_DDR3_A[3] A_DDR3_A[4] B_DDR3_A[4] A_DDR3_A[5] B_DDR3_A[5] A_DDR3_A[6] B_DDR3_A[6] A_DDR3_A[7] B_DDR3_A[7] A_DDR3_A[8] B_DDR3_A[8] A_DDR3_A[9] A_DDR3_A[10] B_DDR3_A[9] B_DDR3_A[10] A_DDR3_A[11] B_DDR3_A[11] A_DDR3_A[12] B_DDR3_A[12] A_DDR3_A[13] B_DDR3_A[13] A_DDR3_A[14] D25 F22 G22 E24 F21 E23 D22 D24 D21 C24 C25 F23 E21 D23 B_DDR3_A[14] B-TMA0 B-TMA1 B-TMA2 B-TMA3 B-TMA4 B-TMA5 B-TMA6 B-TMA7 B-TMA8 B-TMA9 B-TMA10 B-TMA11 B-TMA12 B-TMA13 B-TMA14 : : : : : : : : 4’b0000 4’b0001 4’b0010 4’b0100 4’b0101 4’b0110 4’b1001 4’b1010 Boot from 8051 with SPI flash Secure B51 without scramble Secure B51 with scramble Boot from MIPS with SPI flash Boot from MIPS with SPI flash Boot from MIPS with SPI flash Secure MIPS without scramble Secure MIPS with scramble P19 R16 M14 L402 120-ohm Main L414 Main 120-ohm +3.3V_ST L403 120-ohm Main F13 B15 E13 G20 A_DDR3_BA[0] B_DDR3_BA[0] A_DDR3_BA[1] B_DDR3_BA[1] A_DDR3_BA[2] B_DDR3_BA[2] C17 A17 B16 A12 C12 F20 G25 A_DDR3_MCLK B_DDR3_MCLK A_DDR3_MCLKZ B_DDR3_MCLKZ A_DDR3_MCLKE B_DDR3_MCLKE E14 B12 F24 G23 F25 D20 A_DDR3_ODT B_DDR3_ODT A_DDR3_RASZ B_DDR3_RASZ A_DDR3_CASZ B_DDR3_CASZ A_DDR3_WEZ B25 B24 A24 B_DDR3_WEZ A-TMDQL0 A-TMDQL1 A-TMDQL2 A-TMDQL3 A-TMDQL4 A-TMDQL5 A-TMDQL6 A-TMDQL7 A-TMDQU0 A-TMDQU1 A-TMDQU2 A-TMDQU3 A-TMDQU4 A-TMDQU5 A-TMDQU6 A-TMDQU7 F11 E20 A_DDR3_RESET B_DDR3_RESET B19 C18 K24 A_DDR3_DQSL A_DDR3_DQSLB B_DDR3_DQSL B_DDR3_DQSLB B18 A18 J21 A_DDR3_DQSU A_DDR3_DQSUB B_DDR3_DQSU H24 A_DDR3_DQML B_DDR3_DQML A_DDR3_DQMU B_DDR3_DQMU D17 G15 B21 F15 B22 F14 A22 D15 B_DDR3_DQL[0] B_DDR3_DQL[1] A_DDR3_DQL[2] B_DDR3_DQL[2] A_DDR3_DQL[3] B_DDR3_DQL[3] A_DDR3_DQL[4] B_DDR3_DQL[4] A_DDR3_DQL[5] B_DDR3_DQL[5] A_DDR3_DQL[6] B_DDR3_DQL[6] A_DDR3_DQL[7] B20 C21 E16 A20 D16 C20 L20 L23 A_DDR3_DQL[0] A_DDR3_DQL[1] J24 L24 J23 M24 H23 M23 K23 B_DDR3_DQL[7] G16 F16 J20 B_DDR3_DQSUB E15 A21 K25 G21 A_DDR3_DQU[0] B_DDR3_DQU[0] A_DDR3_DQU[1] B_DDR3_DQU[1] A_DDR3_DQU[2] B_DDR3_DQU[2] A_DDR3_DQU[3] B_DDR3_DQU[3] A_DDR3_DQU[4] B_DDR3_DQU[4] A_DDR3_DQU[5] B_DDR3_DQU[5] A_DDR3_DQU[6] B_DDR3_DQU[6] A_DDR3_DQU[7] B_DDR3_DQU[7] L22 H22 K20 H20 L21 H21 K21 C1415 C1416 C1417 0.1uF 0.1uF 10uF W10 C425 0.1uF W12 AVDD2P5:172mA 0.1uF C440 0.1uF Close to the Main IC AVDD_NODIE:7.362mA C469 0.1uF U19 C471 C427 AVDD33 0.1uF 10uF P7 R7 Close to the Main IC L408 120-ohm Main C473 C474 C475 AU33:31mA 1uF 10uF 0.1uF C442 0.1uF C476 C477 0.1uF 0.1uF T19 B-TMRESETB W19 B-TMDQSL B-TMDQSLB L409 120-ohm Main VDD33_T/VDDP/U3_VD33_2:47mA B-TMDQSU B-TMDQSUB C479 C482 C483 C484 C485 VDD33_NAND 1uF 10uF 10uF 10uF R456 1K READY R453 1K R447 1K READY R439 1K READY R455 1K READY R457 1K R454 1K READY R448 1K R440 1K R463 1K Downloaded from www.Manualslib.com manuals search engine GND_68 GND_69 AVDD_NODIE GND_71 AVDD_DVI_USB_1 GND_73 AVDD_DVI_USB_2 GND_74 GND_70 GND_72 AVDD3P3_MPLL GND_75 AVDD_DMPLL GND_76 DVDD_NODIE GND_78 AVDD_AU33 GND_80 GND_77 GND_79 0.1uF VDDP_1 GND_83 VDDP_2 GND_84 AVDD_LPLL_1 GND_86 GND_85 GND_91 J17 K15 C455 0.1uF AVDD_DDR0_D_1 GND_92 AVDD_DDR0_D_2 GND_93 AVDD_DDR0_D_3 GND_94 AVDD_DDR0_C GND_95 AVDD_DDR1_D_1 GND_97 GND_96 K17 L17 +1.5V_DDR_IN M17 L16 C486 C492 C467 1000pF L412 120-ohm Main C470 C488 C468 0.1uF 1uF 10uF Close to the Main IC GND_EFUSE C493 C494 C497 C498 0.1uF 0.1uF 10uF 10uF GND_105 A23 B17 C23 C22 D14 D18 D19 E22 F8 F19 N22 N21 N20 M22 M21 F10 V15 W16 V8 MAIN GND_103 GND_104 C11 GP4_S7LR GND_100 GND_102 E9 C19 C466 1000pF GND_98 GND_99 GND_101 A5 B-MVREFCA AVDD_DDR1_D_2 AVDD_DDR1_D_3 AVDD_DDR1_C 0.1uF 10uF AVDD_DDR0:55mA AVDD_DDR1:55mA GND_89 GND_90 K16 Close to the Main IC GND_87 GND_88 VDDP_NAND L15 C453 0.1uF B-TMDML B-TMDMU GND_81 GND_82 V19 T18 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AVDD25_PGA AVSS_PGA AVDD_LPLL_2 F18 C465 0.1uF GND_67 Close to the Main IC CLose to Saturn7M IC R492 1K 1% GND_64 GND_65 R19 M20 C464 1000pF AVDD_MOD_1 AVDD_MOD_2 V7 W7 R491 1K 1% C463 0.1uF GND_62 GND_63 W18 PWM0 GND_60 GND_61 AVDD_EAR33 B-TMODT B-TMRASB B-TMCASB B-TMWEB A-MVREFCA R484 1K 1% GND_58 GND_59 M19 H8 LED_RED AVDD2P5_ADC_2 AVDD2P5_ADC_3 U7 M7 C441 0.1uF B-TMCK B-TMCKB B-TMCKE B-TMDQU0 B-TMDQU1 B-TMDQU2 B-TMDQU3 B-TMDQU4 B-TMDQU5 B-TMDQU6 B-TMDQU7 GND_57 L7 VCC_1.5V_DDR PWM1 AVDD2P5_ADC_1 W14 G8 AUD_MASTER_CLK GND_56 GND_66 F17 R483 1K 1% GND_53 GND_54 V18 E19 AUD_SCK AVDD10_LAN DVDD_DDR AVDD25_REF W15 +3.3V VCC_1.5V_DDR GND_51 GND_52 Y17 E17 CLose to Saturn7M IC FB_CORE AVDDL_MOD AVDD25_LAN L413 120-ohm Main L406 +3.3V 120-ohm Main B-TMBA0 B-TMBA1 B-TMBA2 B-TMDQL0 B-TMDQL1 B-TMDQL2 B-TMDQL3 B-TMDQL4 B-TMDQL5 B-TMDQL6 B-TMDQL7 GND_50 W9 W11 C1418 AVDD1P0 GND_55 AVDD25_PGA:13mA C439 0.1uF GND_49 P10 E18 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes RXB1- AA25 VDDC_14 L11 A-TMRESETB C487 10uF 16V READY LVBCKN GPIO194 0.1uF FB_CORE AA23 AE24 LVACKP LVACKN C1412 IC400 LGE2111A-T8 Y24 AA25 LVB4N LVBCKP SOC_RESET V24 W25 K11 P15 Close to the Main IC A-TMCK A-TMCKB A-TMCKE AC24 AE23 0.1uF 0.1uF 0.1uF 10uF 10uF 10uF LOW HIGH V23 GPIO51EU_SPIL_MAIN ICLVB0P GPIO52 VDDC : 2026mA RF_SWITCH_CTL AB23 RXBCK+ AA23 Y24 G9 H9 K10 C1406 C1407 C1408 C1409 C1410 C1411 +1.10V_VDDC DDR PIN NO. AB25 GPIO36 GPIO37 Y24 T25 GPIO193 A9 U24 V25 LVBCKN GPIO194 F7 AB5 AB3 AE24 LVACKP D5 AE23 AC23 LVB4N LVACKN F5 AB24 AD25 V23 GPIO51USA_SPIL_MAIN ICLVB0P GPIO52 AB25 AB23 RXB3+ RXBCK- W23 IC400 LGE2111A-T8 +2.5V 16V F5 B6 E5 GPIO36 V24 W25 AVDDLV_USB SAR3/GPIO34 MODEL_OPT_1 GPIO37 RXB3- K12 SAR1/GPIO32 SAR2/GPIO33 MODEL OPTION SOC_RESET C7 RXB4+ V25 GND_48 TX E6 RXA0+ RXB4- U24 BUF1_FE_TS_DATA[0-7] SAR0/GPIO31 HWRESET IC400-*3 LGE2111A-T8 SPIL RXA0- AD23 BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3] BUF1_FE_TS_DATA[4] BUF1_FE_TS_DATA[5] BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7] PWM4/GPIO70 N4 IC400-*2 LGE2111A-TE SPIL RXA1+ GPIO195 BUF1_FE_TS_CLK BUF1_FE_TS_VAL_ERR BUF1_FE_TS_SYN AD15 AD16 DDCA_DA/UART0_TX DDCA_CK/UART0_RX GPIO196 CI_TS_DATA[0-7] L405 120-ohm Main C426 0.1uF ET_NET ARC0 LVB2P LVB2N CI_TS_DATA[0] CI_TS_DATA[1] CI_TS_DATA[2] CI_TS_DATA[3] CI_TS_DATA[4] CI_TS_DATA[5] CI_TS_DATA[6] CI_TS_DATA[7] AB6 ET_COL/LED0/GPIO55 IRIN/GPIO4 AC23 AC22 AE24 MIUVDDC B5 ET_TX_CLK/TN/GPIO59 AB4 LVB1N GPIO73 GPIO74 SPI2_DI/GPIO204 ET_TXD[1]/LED1/GPIO56 CVBSOUT1 I2C_SDAM0/GPIO54 LVB4P R24 A6 ET_RXD[1]/RN/GPIO63 LVB0N LVB1P SAR4/GPIO35 R25 C6 CVBS3 RXA1- LVB4N CVBS0 CVBS1 LVB0P GPIO52 I2C_SCKM0/GPIO53 LVBCKP EARPHONE_OUTR AA8 RXACK+ AE23 V23 GPIO51 LVACKP AA6 EARPHONE_OUTL R427 33 C422 R428 EU 33EUC423 R429 33 C424 RXA3RXA3+ RXACK- AD25 AC24 T25 CI_TS_CLK CI_TS_VAL CI_TS_SYNC AA10 Y13 TS0DATA_[0]/GPIO77 UART1_RX/GPIO44 PWM0/GPIO66 RXA4+ AB24 H6 KEY1 KEY2 TOUCH_VER_CHK AD5 BIN2M LVA4P LVA4N GPIO50 LVACKN PWM_PM/GPIO199 LED_RED AUVRM SOGIN2 GPIO46 GPIO49 SPI_SCK /SPI_CS SPI_SDI SPI_SDO VSYNC_LIKE/GPIO145 AUVAG LVA3N LVB3N R23 GIN2M GPIO45 USB1_CTL MODEL_OPT_3 READY R487 R432 22 B1 TS0SYNC/GPIO86 PCM2_CD_N/GPIO135 PCM2_WAIT_N/GPIO133 P21 PWM0 PWM1 COMP2_DET SC_RE2 RIN2P BIN2P LVA2N LVA3P AC25 LVBCKN TS0CLK/GPIO87 PCM2_CE_N/GPIO131 PCM2_IRQA_N/GPIO132 D2 D1 HSYNC2 RIN2M GPIO41 GPIO42 RXA4- AB23 Y7 BIN1M GIN2P LVA2P PCMWAIT_N/GPIO100 P23 AMP_MUTE Y2 AA3 LVA1P LVA1N GPIO40 LVB3P AA2 R420 R421 R422 R423 R424 R425 R426 COMP2_Pr+ LVA0N GPIO38 GPIO39 /FLASH_WP M4 D3 AB1 AB25 LVA0P GPIO37 ERROR_DET M5 C1 B2 F4 RF_SWITCH_CTL SCART1_MUTE L5 M6 A2 PM_SPI_CZ0/GPIO_PM[12]/GPIO0 PCMCD_N/GPIO130 A9 MODEL_OPT_1 100 K6 K5 GPIO_PM[11]/GPIO17 PM_SPI_SCK/GPIO1 PCMCE_N/GPIO115 PCMIRQA_N/GPIO105 TS1DATA_[2]/GPIO90 SCART1_Lout 1/16W 22 AE17 PCMADR[6]/GPIO102 UART3_RX/GPIO48 R477 R478 AR400 AD19 PCMADR[7]/GPIO103 D4 N25 B8 I2C_SCL I2C_SDA AC19 F5 5V_DET_HDMI_3 /PF_WP /PF_CE0 /PF_CE1 /PF_OE /PF_WE PF_ALE /F_RB AD17 PCMADR[5]/GPIO101 PCM2_RESET/GPIO134 22 22 R481 R482 UART_TXD UART_RXD S7_TXD S7_RXD R472 2.2K 1/16W 22 AD18 AC18 Y14 T20 U22 EU AA9 NF_CLE/GPIO136 NF_REZ/GPIO139 U21 V21 R471 2.2K PCMADR[0]/GPIO125 PCMADR[1]/GPIO124 AR401 AC17 GPIO36 PCM_RESET/GPIO129 22 EU R458 22 R459 EU R20 HOTPLUGD/GPIO22 AUR0 NF_WPZ/GPIO198 NF_CEZ/GPIO137 PCMIOWR_N/GPIO109 AC20 AUD_LRCK I2S_OUT_WS/GPIO155 AE18 NF_CE1Z/GPIO138 AD21 /PCM_CE E6 5V_DET_HDMI_2 PCMDATA[5]/GPIO118 PCMDATA[6]/GPIO117 PCMADR[14]/GPIO106 /PCM_IRQA C461 C462 0.1uF 0.1uF READY EU 16V 16V PCMDATA[3]/GPIO120 PCMDATA[4]/GPIO119 Y20 SOGIN1 R498 0 NON_EU AA21 +3.3V DDCDD_DA/GPIO30 VSYNC1 AB18 AA20 C7 5V_DET_HDMI_1 AB15 RXD2N DDCDD_CK/GPIO29 V20 W22 AA22 AUD_SCK AUD_MASTER_CLK AUD_LRCH C9 PCMDATA[2]/GPIO128 W20 /PCM_WAIT SUB_SDA SUB_SCL P_SCL D8 B10 I2S_OUT_BCK/GPIO156 RXD1P RXD1N PCMDATA[0]/GPIO126 PCMDATA[1]/GPIO127 PCMDATA[7]/GPIO116 /PCM_OE /PCM_WE /PCM_IORD R476 /PCM_IOWR 10K SOGIN0 V3 U3 AB21 /PCM_REG V2 SC1_ID SC1_FB SC1_R+/COMP1_Pr+ AA15 AE21 +5V E2 I2S_IN_WS/GPIO149 RXD0P RXD0N P2 C401 C402 C403 C404 C405 C406 C407 P_SDA SPDIF_OUT C8 I2S_IN_BCK/GPIO150 RXDCKP CEC/GPIO5 R3 GND_2 R468 3.3K AB22 AE20 DDCDC_CK/GPIO27 AUL0 R404 R405 R406 R407 R408 R409 R410 R411 R412 R466 3.3K 22 100 AC12 RXC2N DDCDC_DA/GPIO28 F2 G3 R461 R488 E3 RXC1P HOTPLUGC/GPIO21 CK+_HDMI1 CK-_HDMI1 D0+_HDMI1 D0-_HDMI1 D1+_HDMI1 D1-_HDMI1 D2+_HDMI1 D2-_HDMI1 DDC_SDA_1 DDC_SCL_1 HPD1 CEC_REMOTE_S7 D6 RXC0P EU AC11 AD10 D7 RXCCKP EU AD9 3 HOTPLUGB/GPIO20 AE9 AC9 AC10 X-TAL_2 C448 AC1 XOUT R5 SC_RE1 CK+_HDMI3 CK-_HDMI3 D0+_HDMI3 D0-_HDMI3 D1+_HDMI3 D1-_HDMI3 D2+_HDMI3 D2-_HDMI3 DDC_SDA_3 DDC_SCL_3 HPD3 2 XIN T23 DSUB_HSYNC DSUB_VSYNC DSUB_R+ +3.3V AD1 U23 T24 GPIO195 1 T25 GPIO196 GPIO193 GPIO194 W21 AA18 PCM_A[0] PCM_A[1] PCM_A[2] PCM_A[3] PCM_A[4] PCM_A[5] PCM_A[6] PCM_A[7] PCM_A[8] PCM_A[9] PCM_A[10] PCM_A[11] PCM_A[12] PCM_A[13] PCM_A[14] HNIM HNIM HOTPLUGA/GPIO19 PCM_D[0] PCM_D[1] PCM_D[2] PCM_D[3] PCM_D[4] PCM_D[5] PCM_D[6] PCM_D[7] IF_N_MSTAR C457 1000pF 50V READY +3.3V IC400 LGE2111A-T8 IF_P_MSTAR C460 100pF 50V HNIM AD4 RXA2P RXA2N LVDS IC400 LGE2111A-T8 PCM_D[0-7] READY HNIM C456 C459 100pF 100pF 50V 50V HNIM 0.1uF C452 100 R451 HNIM AC3 RXA0N W25 LVB2P GPIO73 GPIO74 J3 K3 HNIM 0.1uF R450 100 C451 HNIM J2 CK+_HDMI2 CK-_HDMI2 D0+_HDMI2 D0-_HDMI2 D1+_HDMI2 D1-_HDMI2 D2+_HDMI2 D2-_HDMI2 DDC_SDA_2 DDC_SCL_2 HPD2 AB25 C7 E6 GND_1 GND_106 GND_2 GND_107 GND_3 GND_108 GND_4 GND_109 GND_5 GND_110 GND_6 GND_111 GND_7 GND_112 GND_8 GND_113 GND_9 GND_114 GND_10 GND_115 GND_11 GND_116 GND_12 GND_117 GND_13 GND_118 GND_14 GND_119 GND_15 GND_120 GND_16 GND_121 GND_17 GND_122 GND_18 GND_123 GND_19 GND_124 GND_20 GND_125 GND_21 GND_126 GND_22 GND_127 GND_23 GND_128 GND_24 GND_129 GND_25 GND_130 GND_26 GND_131 GND_27 GND_132 GND_28 GND_133 GND_29 GND_134 GND_30 GND_135 GND_31 GND_136 G11 G12 G13 G14 G17 G18 G19 G24 H11 H12 H13 H14 H15 H16 H17 H18 H19 J9 J10 J11 J12 J13 J14 J15 J16 J18 J19 J25 K9 K13 K14 H10 K18 K19 K22 L8 L9 J8 L12 L13 L18 L19 M8 K8 M10 M11 L14 M15 M16 M18 M25 N10 N11 N13 N14 N15 N16 N17 N19 K7 P8 P9 M9 P11 P13 P16 P17 P18 P12 R8 R9 R11 R12 R13 R17 T8 T9 N7 T11 T12 T13 T14 T15 T16 T17 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 R18 V9 V10 V11 V12 V14 V17 T7 E8 2011-10-20 4 6 LGE Internal Use Only K2 K8 0.1uF N1 C529 0.1uF N9 C530 0.1uF R1 C531 0.1uF R9 C532 0.1uF C533 0.1uF VDD_3 A11 VDD_4 A12/BC VDD_5 C9 E9 VREFCA H9 A1 A2 H1 A3 VREFDQ A4 A5 L8 A6 CK VDDQ_6 H2 M8 A0 ODT RAS VDDQ_9 CAS D9 VDD_2 A15 K2 K8 VDD_7 BA0 J9 R1 R9 VDD_9 NC_2 BA1 M3 BA2 A1 VDDQ_1 J7 CK K7 CK K9 C1 VDDQ_3 CKE C9 VDDQ_4 CS H2 H9 RESET NC_2 DQSL NC_6 J9 L1 NC_3 L9 NC_4 A-TMA14 T7 DQSL C7 VSS_1 DQSU NC_6 F7 DQL1 F2 DQU0 A3 D1 VSSQ_3 D8 VSSQ_4 E2 VSSQ_5 VSSQ_6 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 E1 E8 F9 G1 J2 SS_1G_1600 J8 IC501-*2 K4B1G1646G-BCK0 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 A1 A2 L8 ZQ A8 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 NC_5 VDD_7 VDD_8 BA0 D9 G7 P9 K2 K8 N1 N9 R1 T1 R9 VDD_9 BA1 BA2 A1 VDDQ_1 CK VDDQ_2 CK VDDQ_3 CKE VDDQ_4 VDDQ_5 CS VDDQ_6 ODT VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 WE A8 T9 C1 C9 D2 VSS_2 DQSU E9 F1 H2 RESET NC_2 DQSL NC_6 NC_3 NC_4 VSS_5 DMU C7 B7 VSS_7 DQL0 VSS_8 DQL1 VSS_9 DQL2 VSS_10 DQL3 VSS_11 DQL4 VSS_12 DQL5 DQL6 J9 L9 T7 VSS_1 VSS_2 VSS_3 DML VSS_4 DMU F7 F2 F8 H3 H8 G2 H7 VSS_5 VSS_6 DQL0 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 VSS_12 DQL7 B8 A3 B3 E1 17 20 21 G3 A-TMDQSLB 22 23 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 D8 E2 G1 G9 B7 24 A-TMDQSUB HD A-TMDML D3 F9 G1 G9 P3 F7 N2 P8 F2 A-TMDQL1 A-TMDQL2 T8 A-TMDQL3 M7 P2 R8 R2 R3 L7 R7 N7 F8 T3 VREFCA A-TMDQL4 A1 P3 A2 A-TMDQL5 A-TMDQL6 H7 A-TMDQL7 VDD_7 VDD_8 14 15 DQU3 VSSQ_6 DQU4 DQU5 VSSQ_8 DQU6 K9 F7 F2 F8 G2 H7 RESET NC_2 DQSL NC_6 NC_4 A2 R504 ZQ C506 D9 0.1uF G7 0.1uF K2 C509 0.1uF K8 C510 C508 0.1uF N1 C511 0.1uF N9 C512 0.1uF R1 R9 C513 0.1uF C514 0.1uF C515 0.1uF A8 VDD_1 A9 VDD_2 A10/AP VDD_3 A11 VDD_4 A12/BC VDD_5 VDD_7 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 A3 L8 ZQ A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 VDD_6 VDD_7 VDD_8 M2 N8 M3 BA0 H2 R9 A1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 CS ODT VDDQ_6 VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 WE RESET NC_2 NC_3 NC_4 F3 DQSL A8 H9 C1 C9 D2 DQSU VSS_1 VSS_2 VSS_3 DML VSS_4 VSS_5 VSS_6 DQL0 NC_2 NC_6 NC_3 F3 A9 G3 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 VSS_12 NC_4 33 VSS_1 DQSU VSS_2 VSS_3 DML VSS_4 DMU VSS_5 VSS_6 F8 H3 H8 G2 H7 DQL0 VSS_7 DQL1 VSS_8 C3 C8 C2 A7 A2 B8 A3 DQL2 DQL3 DQL4 DQL5 J9 VSS_9 VSS_10 VSS_11 E1 G8 J2 L1 J8 M1 M9 P1 P9 L9 T1 T9 VSS_12 B1 VSSQ_1 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 B9 D1 D8 B-TMA14 E2 E8 P8 P2 R8 R2 T8 R3 L7 35 C9 D2 36 E9 F1 H2 H9 37 J9 L1 L9 38 T7 B7 B3 DQSU VSS_1 DQSU VSS_2 E1 VSS_3 E7 G8 D3 J2 DML VSS_4 DMU E3 M9 F7 F2 P1 F8 P9 H3 T1 H8 T9 G2 H7 VSS_5 VSS_6 DQL0 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 VSS_12 R7 N7 T3 H1 VREFDQ L8 ZQ B2 VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 VDD_6 M7 NC_5 VDD_7 VDD_8 M2 N8 M3 BA0 J2 G7 K2 K8 N1 J8 N9 R1 M1 A1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 CS ODT VDDQ_6 VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 WE A8 C1 C9 D2 M9 E9 F1 H2 H9 P1 J1 NC_1 T2 RESET NC_2 NC_3 NC_4 F3 G3 R9 VDD_9 VDDQ_1 CK CK CKE L2 K1 J3 K3 L3 D9 BA1 BA2 J7 K7 K9 G8 A4 A5 A6 A7 A8 A9 DQSL J9 L1 L9 T7 P9 NC_6 DQSL C7 B7 A9 DQSU VSS_1 DQSU VSS_2 VSS_3 E7 D3 DML VSS_4 DMU VSS_5 VSS_6 E3 F7 F2 F8 H3 H8 G2 H7 DQL0 VSS_7 DQL1 VSS_8 DQL2 DQU6 VSSQ_8 DQU7 VSSQ_9 C3 C8 C2 A7 A2 B8 G9 A3 DQU0 VSSQ_2 DQU1 VSSQ_3 DQU2 VSSQ_4 DQU3 VSSQ_5 DQU4 VSSQ_6 DQU5 VSSQ_7 B3 39 E1 G8 J2 J8 40 M1 M9 P1 P9 T1 T9 C3 C8 C2 A7 A2 B8 DQL3 DQL4 DQL5 VSS_9 VSS_10 VSS_11 E1 T1 G8 J2 J8 M1 M9 T9 P1 P9 T1 T9 VSS_12 CAS DQU1 DQU2 DQU3 DQU4 DQU5 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 DQU6 VSSQ_8 DQU7 VSSQ_9 B9 D1 DQSU +1.5V_DDR_IN VSS_5 P3 N2 C545 0.1uF 16V G1 G9 12 37 13 36 14 35 15 34 16 33 17 32 18 31 30 29 28 21 27 22 26 23 24 25 PCM_A[4] NC_25 NC_24 C554 10uF NC_23 VCC_2 VSS_2 C555 0.1uF NC_22 NC_21 NC_20 AR519 22 I/O3 PCM_A[3] IC504-*1 K9F1G08U0D-SCB0 I/O2 PCM_A[2] I/O1 PCM_A[1] I/O0 PCM_A[0] SS NC_1 NC_2 NC_3 NC_4 NC_5 R/B RE NC_19 NC_7 NC_8 VCC_1 VSS_1 NC_18 NC_9 NC_10 NC_17 ALE WE NC_16 NC_11 NC_12 NC_13 ZD501 NC_15 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 NC_29 NC_28 NC_27 NC_26 I/O7 I/O6 I/O5 I/O4 NC_25 NC_24 NC_23 VCC_2 VSS_2 NC_22 NC_21 NC_20 I/O3 I/O2 I/O1 I/O0 NC_19 NC_18 NC_17 NC_16 R8 37 38 39 G9 40 41 FHD RXA1+ 44 50 45 RXA2- 51 46 RXA2+ CS /SPI_CS 1 8 2 7 3 6 GND 4 5 8 2 7 3 6 4 5 C556 0.1uF VCC VCC DO[IO1] HOLD# SPI_SDO WP# 1 HOLD[IO3] SCLK R561 0 SI/SIO0 %WP[IO2] /FLASH_WP GND 47 CLK SPI_SCK R575 DI[IO0] 33 SPI_SDI RXACK- 49 RXACK+ 50 RXA3- 51 RXA3+ RXA4RXA4+ 55 56 RXB0- 57 RXB0+ 58 B-TMA6 59 B-TMA7 B-TMA9 L7 B-TMA10 RXB1RXB1+ 60 R7 B-TMA11 N7 B-TMA12 T3 B-TMA13 RXB2- 62 RXB2+ 64 65 B-TMCKB B-TMBA0 B-TMBA1 B-TMBA2 61 A0’h EEPROM 1MBit +3.3V 63 RXBCKRXBCK+ RXB3- 67 RXB3+ 68 RXB4- A2 69 RXB4+ VSS A1 8 2 7 3 6 4 5 C552 0.1uF VCC WP IC503 AT24C256C-SSHL-T SCL SDA A0 A1 72 A2 74 75 76 77 B-TMODT B-TMRASB K3 B-TMCASB L3 B-TMWEB 8 2 7 3 6 4 5 VCC WP SCL R573 22 SDA R574 22 73 C542 0.01uF 50V B-TMCKE 1 71 R510 56 1% R508 56 1% IC503-*1 R1EX24256BSAS0A Renesas_IC503 A0 1 66 70 K7 J3 SO/SIO1 R569 4.7K READY 54 B-TMA8 K1 RXA0+ RXA1- 43 53 R3 K9 MX CS# RXA0- 42 52 R2 M3 +3.3V_ST IC505 W25Q80BVSSIG R564 10K IC505-*1 MX25L8006EM2I-12G 49 B-TMA0 T8 N8 +3.3V_ST +3.3V_ST 36 B-TMA3 B-TMA4 SERIAL FLASH 8MBit 35 43 B-TMA1 B-TMA5 VCC_1.5V_DDR I2C_SCL P_SDA GND DISP_EN 78 P_SCL PC_SER_DATA 79 PC_SER_CLK I2C_SDA 80 R507 10K 81 B-TMRESETB B-TMDQSL G3 B-TMDQSLB SS_1G_1333 SS_2G_1333 IC500-*3 K4B1G1646G-BCH9 B-TMDQSUB N3 P2 B-TMDML R8 R2 T8 R3 L7 D3 B-TMDMU E3 B-TMDQL0 R7 N7 T3 A11 A12/BC A13 VSS_11 DQL4 VSS_12 DQL5 VSSQ_2 DQU0 VSSQ_3 DQU1 VSSQ_4 DQU2 VSSQ_5 DQU3 VSSQ_6 DQU4 VSSQ_7 DQU5 VSSQ_8 DQU6 VSSQ_9 DQU7 VDD_3 VDD_4 VDD_5 VDD_7 VDD_8 K2 K8 F1 H2 H9 B-TMDQL4 D3 DML DMU F8 H3 H8 G2 H7 DQL0 DQL1 VSS_4 VSS_5 VSS_7 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 DQL5 C8 C2 B-TMDQU0 C3 B-TMDQU1 C8 B-TMDQU2 C2 B-TMDQU3 A7 B-TMDQU4 A2 B-TMDQU5 B8 B-TMDQU6 A3 B-TMDQU7 A2 B8 A3 VSS_11 K2 K8 N1 N9 +3.3V R1 R9 VDD_9 BA1 BA2 A1 VDDQ_1 CK CK CKE VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 CS ODT VDDQ_6 VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 WE NC_2 NC_3 NC_4 DQSL A8 C1 C9 D2 E9 F1 H2 H9 J1 NC_1 RESET G8 J2 J9 L1 L9 T7 NC_6 VSSQ_8 VSSQ_9 VSS_3 VSS_4 VSS_5 VSS_6 DQL0 DQL1 VSS_7 VSS_8 DQL2 VSS_9 DQL3 C8 C2 A7 A2 G1 B8 G9 A3 VSS_10 DQL4 DQL5 VSS_11 B3 IC502 CAT24C08WI-GT3-H-RECV(TV) E1 G8 J2 J8 M1 M9 R563 4.7K P1 P9 T1 T9 VSS_12 DQL6 DQL7 D7 C3 D8 E2 E8 DML DMU H3 H8 B9 D1 F9 VSS_1 VSS_2 E3 F7 F2 F8 T1 T9 G2 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 DQU6 DQU7 A9 DQSU DQSU E7 D3 J8 M1 M9 P1 P9 H7 VSSQ_2 VSSQ_3 DQU2 DQU3 DQU4 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 BA0 F3 C7 B1 DQU0 DQU1 DQU5 A13 NC_5 K1 J3 K3 T2 B7 VSS_12 VSSQ_1 D7 C3 A7 B-TMDQL7 D7 A11 A12/BC J7 K7 K9 L2 A9 B3 E1 DQL6 DQL7 B-TMDQL6 H7 L8 B2 D9 G7 DQSL VSS_6 E3 F7 F2 B-TMDQL5 G2 H1 ZQ VDD_1 VDD_2 L9 T7 G3 VSS_1 VSS_2 VSS_3 E7 H3 H8 N7 L3 J9 L1 NC_6 VREFCA VREFDQ A4 A5 A6 A7 A8 A9 A10/AP M7 M3 NC_4 DQSU DQSU M8 A0 A1 A2 A3 M2 N8 A8 C1 C9 D2 E9 J1 NC_1 NC_2 NC_3 DQSL DQSL C7 B7 T3 N1 N9 R1 R9 A1 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 RESET F3 G3 L7 R7 VDD_9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 CS ODT RAS CAS WE T2 R3 D9 G7 BA1 CK CK CKE K1 J3 K3 L3 B-TMDQL3 DQL7 VSSQ_1 P2 R8 R2 T8 BA2 B-TMDQL1 B-TMDQL2 F8 N2 P8 L8 B2 VDD_6 NC_5 BA0 J7 K7 K9 L2 F7 F2 N3 P7 P3 H1 ZQ VDD_1 VDD_2 M7 M3 DQL2 DQL3 VREFCA VREFDQ A4 A5 A6 A7 A8 A9 A10/AP M2 N8 DQL1 VSS_9 VSS_10 IC500-*4 K4B2G1646C M8 A0 A1 A2 A3 Addr:10101-- HDCP EEPROM 8KBit B-TMDQSU B7 DMU DQL0 VSS_8 DQL6 C544 10uF 10V 38 20 NC_12 R567 1K 34 B-TMA2 P8 P2 N2 VSS_6 B1 F9 L500 500 Main P7 P8 VSS_7 D1 E8 11 PCM_A[5] I/O4 33 48 P7 D8 VCC_1.5V_DDR 39 PCM_A[6] I/O5 NC_14 32 42 A-TMDQU7 E7 DML E2 D8 40 10 PCM_A[7] I/O6 WP 31 44 P3 VSS_3 VSS_4 E8 E2 NC_11 NC_15 30 41 48 C7 DQSU VSS_2 F9 D1 41 9 AR518 22 I/O7 NC_6 R558 0 NC_14 29 D8 47 F3 DQSL VSS_1 G1 B9 42 8 PCM_A[0-7] NC_26 NC_3 NC_4 B9 G9 7 19 /PF_WP NC_13 E2 E8 F9 46 T2 B1 VSSQ_1 DQU0 WP 43 28 RXB2RXB2+ RXBCKRXBCK+ RXB3RXB3+ RXB4RXB4+ G1 45 RESET DQL6 DQL7 D7 A3 B3 WE /PF_WE 44 27 B1 VSSQ_1 D7 B9 D1 D8 E2 E8 F9 G1 A-TMDQU5 DQSL E1 VREFCA ALE PF_ALE DQL6 DQL7 B1 VSSQ_1 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 A-TMDQU6 WE NC_2 NC_6 B3 A1 A2 A3 T7 F9 M8 A0 RAS NC_1 A9 N3 P7 CS ODT G1 IC500-*2 K4B1G1646G-BCK0 P3 VDDQ_6 VDDQ_7 VDDQ_8 /PF_CE1 45 6 NC_27 25 L2 G9 SS_1G_1600 N2 VDDQ_5 J1 L1 L9 T7 B3 DQL6 DQL7 D7 CK CKE VDDQ_9 E9 F1 H2 CLE 46 5 NC_28 26 34 R1 R9 A8 C1 A9 J8 M1 DQL6 DQL7 A3 RESET DQSL L1 C7 D9 G7 K2 K8 N1 J1 NC_1 T2 J9 RXB0RXB0+ RXB1RXB1+ J7 CK VDDQ_3 H9 A9 DQSU E7 D3 E3 F7 F2 NC_9 NC_10 R556 3.3K N9 A1 L9 T7 32 B2 VDD_8 A-TMDQU4 M2 BA0 VDDQ_4 J9 NC_6 DQSL C7 B7 VSS_1 9 3 4 NC_29 23 VDD_9 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 B8 A3 BA2 VDDQ_2 VCC_1 8 47 22 B-TMCK VDDQ_1 J1 NC_1 T2 G3 F1 VDD_9 VDDQ_1 CK CK CKE L2 K1 J3 K3 D9 G7 K2 K8 N1 N9 R1 BA1 BA2 J7 L3 E9 B2 VDD_1 A15 K7 D2 H1 VREFDQ A4 A5 A6 A7 A8 A9 M7 K9 C9 VREFCA NC_8 21 M7 BA1 C1 M8 A0 A1 A2 7 20 NC_5 VDD_8 A1 IC500-*1 H5TQ1G63DFR-PBC N3 CE 48 2 CLE L8 ZQ VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDDQ_1 VDDQ_2 VDDQ_3 CKE CS ODT RAS CAS A2 A13 VDD_6 VDD_9 A8 Hynix_1G_1600 A6 A7 10uF C507 P7 A3 A5 L8 240 1% B2 P3 A0 A4 C502 C500 0.1uF 1000pF RE NC_7 R566 1K READY C550 0.1uF 19 31 H1 VREFDQ A9 A10/AP A11 A12/BC BA0 DQSL D7 C3 C8 C2 A7 B8 DQU7 A1 VREFDQ /F_RB /PF_OE /PF_CE0 6 18 BA1 CK CK L2 K1 J3 K3 L3 DQSL A2 A-TMDQU3 J7 K7 C9 D2 E9 F1 H2 H9 J1 NC_1 T2 H3 C2 A8 C1 WE F3 H8 A7 N3 VREFCA H1 NC_6 5 17 RXACKRXACK+ RXA3RXA3+ RXA4RXA4+ A1 A2 A3 NC_5 M2 N8 BA2 DMU M8 B-MVREFDQ R568 4.7K R/B C520 10pF 50V C522 10pF R520 50V 100READY C523 10pF 50V READY NC_5 R565 1K 4 1 CE VCC_1.5V_DDR B-MVREFCA NC_4 3 16 52 R500 1K 1% A1 MULTI 13 IC500 H5TQ1G63DFR-H9C R501 1K 1% R514 22 NC_3 2 A4 A5 A6 A7 A8 A13 M7 R1 R9 M3 C7 A-TMDQU1 A-TMDQU2 R7 N7 T3 VREFCA A1 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 E3 A-TMDQU0 C8 R3 L7 D9 G7 K2 K8 M8 A0 N1 N9 VDD_9 VDDQ_2 CK CKE CS ODT RAS CAS NC_3 C3 R2 T8 B2 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDDQ_1 CK WE G3 P8 P2 R8 L8 ZQ A8 A9 A10/AP A11 A12/BC BA0 BA1 BA2 K9 L2 K1 J3 K3 L3 N2 H1 VREFDQ A3 A4 A5 A6 NC_5 N8 M3 J7 K7 H8 G2 P7 A7 A13 M2 H3 30 N3 M8 A0 E7 VSSQ_7 SS_2G_1333 N3 P7 29 IC501-*4 K4B2G1646C IC501-*3 K4B1G1646G-BCH9 A-TMDQL0 D3 DQU1 DQU2 VSSQ_9 C 12 RXA2RXA2+ SUB_SDA R539 4.7K R519 100 NC_2 24 27 28 A-TMDMU D7 DQU0 VSSQ_3 VSSQ_4 VSSQ_5 E8 +3.3V_ST C534 220pF 50V +3.3V C547 0.1uF 16V 11 25 DQSU VSSQ_2 D1 B9 D1 D8 E2 E8 F9 A-TMDQSU B7 B9 M9 P1 P9 T1 T9 B1 VSSQ_1 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 10 RXA0RXA0+ RXA1RXA1+ SUB_SCL UART_RXD UART_TXD 7 15 A-TMDQSL DQL7 VSSQ_1 G8 J2 J8 M1 DQL6 D7 C3 C8 C2 A7 A2 B1 A9 DQSU DQSU E7 D3 R506 10K A-TMRESETB E3 H9 L1 C535 220pF 50V LED_RED IC504 H27U1G8F2BTR-BC NC_1 1 26 DML DQSL E3 13 14 A-TMWEB E7 VSS_4 J1 NC_1 T2 F3 G3 P1 B2 VDD_1 A9 A10/AP A11 A12/BC A13 K9 L2 K1 J3 K3 L3 M9 H1 VREFDQ A3 A4 A5 A6 A7 M7 M2 N8 M3 12 VCC_1.5V_DDR SS_1G_1333 VREFCA J7 K7 DQSU VSS_6 M1 M8 N3 VSS_1 VSS_3 G9 G8 A0 A-TMCASB C7 B3 B9 VSSQ_2 DQU1 DQU2 DQU3 DQU4 DQU5 A-TMRASB K3 L3 F3 DQSL A9 B1 VSSQ_1 D7 C3 C8 C2 A7 A2 A-TMODT J3 M9 T1 T9 DQL6 DQL7 B8 0 11 K1 P1 P9 VSS_10 VSS_11 VSS_12 0 R537 5 8 J2 VSS_9 DQL3 DQL4 DQL5 R536 4 READY 0 7 M1 VSS_8 DQL2 F8 H3 H8 G2 3 4 J8 VSS_6 H7 +3.3V_ST 3 R576 6 C543 0.01uF 50V A-TMCKE DQSL E1 G8 VSS_4 VSS_5 VSS_7 R511 56 1% 2 6 K9 T2 NC_4 T7 B3 VSS_2 VSS_3 DML DMU DQL0 R509 56 1% K7 RESET A9 DQSU B7 E7 D3 E3 A-TMBA1 A-TMBA2 1 2 19 J1 NC_1 T2 F3 G3 L9 F1 VDDQ_7 VDDQ_8 VDDQ_9 N8 M3 1 NC_3 E9 VDDQ_6 ODT RAS CAS WE 9 E Q500 MMBT3904(NXP) 47K R578 R538 4.7K 18 D2 VDDQ_5 L2 K1 J3 K3 L3 L1 A8 VDDQ_2 A-TMBA0 R542 10K R517 100 R516 100 KEY2 2K R579 P500 104060-8017 A-TMCK A-TMCKB 16 NC_1 N1 N9 VDD_8 M2 N8 J1 G7 VDD_3 VDD_4 VDD_5 VDD_6 8 R540 10K KEY1 C B P503 TF05-51S WE B2 VDD_1 A9 A10/AP A11 A12/BC A13 A-TMA13 L2 CS VDDQ_7 VDDQ_8 ZQ A8 R3 L7 R7 N7 T3 A-TMA11 A-TMA12 T3 CKE A7 M7 R7 N7 5 CK VDDQ_3 VDDQ_5 F1 IC501-*1 H5TQ1G63DFR-PBC P3 N2 P8 P2 R8 9 10 D500 KDS184 J7 VDDQ_2 VDDQ_4 D2 T8 A-TMA10 BA2 VDDQ_1 A8 C1 N3 A-TMA9 M2 BA0 C517 10pF 50V LD500 A-TMA8 L7 M7 BA1 A1 Hynix_1G_1600 A-TMA7 T8 R3 NC_5 VDD_8 VDD_9 A-TMA6 R2 A13 VDD_6 VDD_7 A-TMA5 R8 +3.3V_ST 10V G7 0.1uF 0.1uF C528 A9 IR NAND Flash 1GBit +3.3V R515 4.7K R518 100 ZD503 A8 A10/AP P501 12507WS-08L USA ZD507 ZD506 0.1uF C526 C527 C525 A6 A7 VDD_1 VDD_2 A-TMA4 +3.3V_ST 5.48VTO5.76V ZD505 ZD504 ZQ D9 10uF P8 P2 Key/IR 5.48VTO5.76V A5 L8 B2 C524 A-TMA3 +5V ZD500 R505 240 1% C503 C501 0.1uF 1000pF A-TMA2 N2 +5V ZD502 5.48VTO5.76V 5.48VTO5.76V 5.48VTO5.76V 5.48VTO5.76V 5.48VTO5.76V A4 R503 1K 1% R2 A3 LVDS 5.48VTO5.76V VREFDQ A-TMA1 R513 4.7K A2 H1 A-TMA0 P7 P3 A2 MMBD6100 D500*-1 DDR3 Memory 1GBit x 2 N3 R577 4.7K A1 A-MVREFDQ P7 A0 R512 4.7K VREFCA A2 R502 1K 1% A1 M8 A-MVREFCA C IC501 H5TQ1G63DFR-H9C VCC_1.5V_DDR VSSQ_2 VSSQ_3 DQU2 DQU3 DQU4 DQU5 NC_1 1 NC_2 2 B1 VSSQ_1 DQU0 DQU1 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 8 VCC 7 WP 6 SCL R571 22 SDA R572 22 B9 D1 D8 E2 E8 F9 G1 G9 A2 3 VSS 4 READY 5 R570 4.7K I2C_SCL I2C_SDA * LCI: LVDS Connection Indicator THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine GP4_S7LR Memory.LVDS,IR 2011-10-20 5 6 LGE Internal Use Only C629 10uF 16V C630 0.1uF 16V R622 0 C604-*1 1uF 10V 1 C601 0.1uF 16V GND 3 2 1 MULTI C605 10uF 6.3V C604 1uF 6.3V GND VOUT IC602 AP1117EG-13 FNIM IN C612 10uF 6.3V +3.3V_TU +3.3V +1.25V_TU +3.3V L613 120-ohm 2A DVB_T2 R612 1 L604 120-ohm 2A C671 10uF 10V DVB_T2 C682 0.1uF 16V DVB_T2 C617 10uF 6.3V FNIM ADJ/GND OUTPUT R1 R2 R618 240 FNIM C627 10uF 6.3V R620 1 FNIM R648 120K +5V LX2_2 GND_2 25 11 LX2_1 GND_3 26 10 LX1_2 GND_4 27 9 LX1_1 GND_5 28 8 VIN1 IC605 TPS65253RHDR 1 DCON_EN L606 CIS21J121 RLIM2 SS2 CMP2 EN2 15 16 PGOOD R630 3K 1% C631 10uF 6.3V Vout=1.25*(1+R2/R1) Audio AMP +3.3V FB2 VIN2 12 R631 390K 1% R621 1 Vout=1.25*(1+R2/R1) 17 BST2 13 24 R2 R656 47K 1% C656 22uF 16V C651 22uF 16V L607 NR5040T3R3N C666 0.022uF 16V R657 43K 1% +1.5V_DDR_IN R1 L608 NR5040T3R3N +1.10V_VDDC C683 22uF 16V C653 10uF 25V C654 10uF 25V C652 0.047uF 25V C657 22uF 16V R653 4.3K 1% C661 0.022uF 16V R654 51K 1% R1 R655 100K 1% R2 R658 0 READY FB_CORE +1.8V_TU R1 C625 10uF 6.3V FNIM 18 14 23 [EP]GND IC604 R2 AZ1117BH-ADJTRE1 INPUT OUT ADJ/GND LOW_P 22 C645 IC601 TJ3940S-2.5V-3L VIN VOUT 3.3V_TU /1.8V_TU 220 100 R614 R613 5% 5% 2 +2.5V_TU +2.5V +3.3V +3.3V_ST IC600 AP2121N-3.3TRE1 VIN 3 C600 10uF 10V 1.25V_TU 2.5V Multi/2.5_TU R615 1 FNIM 3.3Vst V7V V3V Vout=0.765*(1+R1/R2) R670 4.7 READY C609 3300pF READY C655 0.047uF 25V GND_1 7 C650 10uF 16V GND BST1 5 C626 3300pF 50V 6 SS C624 1uF 10V EN1 R2 R619 17.4K 1% R649 33K READY DCON_EN 6 4 L605 NR5040T2R2N 2.2uH C628 4700pF 50V 5 3 SW 4 7 SS1 2 RLIM1 VREG5 R650 33K VBST R647 100K C623 22pF 50V C632 4.7uF 10V +3.3V 19 +5V_ST 1.5V DDR / 1.24V Core R634 56K VIN 0.01uF AC_DET C607 0.1uF 16V 8 19 VFB 1 C649 C603 0.1uF 16V READY R1 R617 59K 1% 20 18 EN +5V_ST 21 16 17 R639 3300pF 10K THERMAL 29 15 5V_ON C636 3 RL_ON C641 C634 10uF 16V 2 14 IC603 TPS54327DDAR [EP]GND FB1 13 R609 100 C606 0.1uF 16V C621 0.1uF 50V C610 0.1uF 16V CMP1 12 C608 10uF 10V ROSC 10 C620 10uF 25V R661 10K ERROR_DET 100pF READY 9 11 R600 10K C613 10uF 25V READY +5V L600 120 R635 3300pF 10K 8 0.01uF READY 100pF C648 4 6 7 9 2 3 5 C642 P_17V THERMAL 1 +3.3V_ST C602 0.1uF 16V READY +3.3V Multi P_17V P600 SMAW200-H18S1 DCON_EN Power Wafer R662 56K C611 3300pF 50V READY R666 4.7 READY Vout=0.8*(1+R1/R2) EMI GND R608 0 R628 10K READY R607 0 VDD_DIG_1 GND_DIG_1 AC_DET 22 R638 R625 PWRDN 2.2 VDD_PLL R629 2K C633 0.1uF 16V R626 0 AUD_MASTER_CLK READY AUD_SCK READY AUD_LRCK READY AUD_LRCH READY C637 4700pF 50V C647 680pF 50V FILTER_PLL GND_PLL C635 22pF 50V C639 22pF 50V C640 22pF 50V C644 22pF 50V 22 R640 XTI 22 R641 BICKI 22 R642 LRCKI 22 R643 SDI AMP_RESET_N 22 R644 R623 2K RESET 2K INT_LINE R646 22 SDA AMP_SCL SCL R633 10K C638 0.1uF 50V GND_DIG_2 C646 0.1uF 50V VDD_DIG_2 18 20 17 21 16 22 15 23 14 24 13 12 25 26 11 27Close-by Close-by 10 28 9 29 8 30 7 Close-by 31 6 32 5 33 34 THERMAL R645 22 AMP_SDA R624 19 4 3 35 2 36 Close-by 1 OUT3A/FFX3A R605 0 EMI_GND1 OUT3B/FFX3B R606 0 CONFIG C660 0.1uF 50V VDD R604 0 GND_REG OUT1A GND1 L609 10.0uH C662 1uF C663 VCC1 25V C669 0.1uF 50V 330pF 50V C672 0.22uF 50V L610 10.0uH C674 0.22uF 50V C678 1000pF 50V C675 0.22uF 50V C679 1000pF 50V 4 3 OUT1B L611 10.0uH C670 C664 1uF 25V 330pF 50V C665 0.1uF 50V OUT2A VCC2 L612 10.0uH GND2 P_17V OUT2B VCC_REG C659 0.1uF 50V C667 0.1uF 50V 2 C673 0.22uF 50V C676 0.22uF 50V C680 1000pF 50V C677 0.22uF 50V C681 1000pF 50V EMI_GND2 R602 0 1 SMAW250-H04R P601 EAPD/OUT4B TWARN/OUT4A 39 R685 Q600 MMBT3904(NXP) READY R637 0 R686 39 E C643 0.1uF 50V 39 R687 B READY READY R688 39 AMP_MUTE C 37 R627 10K R636 0 R601 0 EMI_GND3 R603 0 EMI_GND4 GND C668 68uF 35V VSS TEST_MODE SA GND_SUB [EP]GND STA368BWG IC606 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine GP4_S7LR Power,AMP 2011-04-01 6 LGE Internal Use Only Downloaded from www.Manualslib.com manuals search engine GP2R, LM1 Training Manual Table of contents 1. PCB layout. 2. GP2R vs LM1 3. GP2R. (Block, Power, I2C) 4. LM1. (Block, Power, I2C) 5. LM1 SOC Power sequence. 6. Memory test. 7. Pen touch overview. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 1. PCB Layout. GP2R (206 x 183) LM1 (206 x 141.5) ※ LM1 use internal EDID&HDCP. (LM1 is Removing the EEPROM for EDID&HDCP) LM1 is optimizing Power block. (LM1 is reducing DC/DC, LDO, power application) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 2. GP2R vs GP4 LM1. Difference GP2R 50PZ550 LM1 50PA6500 PDP Module R3(FHD) R4(FHD) New module. 50R4 Initial model. Tool PZ Tool PA Tool 12’ years New tool. PCB 206x183 206x141.5 Main IC S7R S7LR Jack Layout Slim Depth Slim Depth Sub Assy PZ Tool PA Tool GP2R 15pin, LM1 8pin PSU 50R3 XP5 B’d 50R4 UP1 B’d Reduce power on time. SW GP2R LM1 PDP only code. JIG GP2R LM1 Support DFT JIG. - . . Power Wafer 18P 18P VSC Changes change PCB Size. (smaller than GP2R.) Internal sub-Micom .(PM block) Same. Develop new WAFER and CABLE. (12 years) Stand by 0.3W ↓ Stand by 3.5V O O Stand by 3.5V . 12V_secondary X X Not use 12V. IR Wafer 15P 8P LM1 not support 3D. USB O O SIDE USB. Memory DDR3 DDR3 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine DDR3 1Gbit . 2ea LGE Internal Use Only 3. GP2R Power measure Summary Power Line Voltage Spec [V] Voltage [V] +5V_ST 4.845~5.355 +5V_ST_EN Ripple [mV] Current [A] 5.01 86 0.009 4.845~5.355 5.00 17 0.710 +3.3V_AVDD 3.14~3.6 3.31 15 0.285 +2.5V_AVDD 2.38~2.62 2.53 20 0.200 +1.5V_DDR_IN 1.425~1.575 1.57 20 0.310 +1.26V_VDDC 1.2~1.32 1.27 30 0.770 +3.3V_ST 3.234~3.366 3.30 19 0.024 +17V 16.15~17.85 17.03 1.09A 1.420 +5V_TU 4.75~5.25 4.99 20 0.170 +5V 4.845~5.355 5.03 57 2.600 +3.3V_TU 3.15~3.46 3.26 None 26 0.320 +1.2V_TU 1.20~1.32 1.27 None 21 0.300 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine Ripple spec [Vpp] 0.5 1.5V +/-5% 0.5 None Remark LGE Internal Use Only 3-1. GP2R Power Block Diagram 5Vst L603 MAX 3A IC205 AT24C02BN RGB EDID +5V_ST C619 100u 16V C627 0.1u 16V C219 0.1u 16V C654 22u 16V +5V_ST_EN Q600 C657 RTR030P02 C656 C655 0.01u 25V 100u 16V 0.1u 16V IC600 AZ1085S 3.3V C600 0.1u 16V C607 22u 6.3V C608 0.1u 16V L602 2A +3.3V_AVDD 2A/3ea C615 0.1u 16V S7_3.3V_AVDD 10u 2ea 0.1u 13ea NAND Flash/HDCP/EEPROM +2.5V_AVDD 2A 2A/2ea IC604 TJ3964 C616 C623 0.1u 16V 22u 6.3V C609 10u 16V C611 0.1u 16V IC602 TPA54319 10u 1ea +1.5V_DDR_IN C637 10u 10V C647 10u 10V C650 0.1u 16V 2A/2ea C610 10u 16V C612 0.1u 16V IC603 TPA54319 2.5V_AVDD 0.1u 4ea 10u 2ea 0.1u 32ea 10u 4ea 0.1u 10ea DDR S7 AVDD_DDR +1.26V_VDDC C651 10u 10V C652 10u 10V C653 0.1u 16V 2A/2ea 10u 2ea 0.1u 2ea 10u 1ea 0.1u 8ea DVDD VDDC IC203 MAX3232CDR IC601 AP2121N 300mA C601 0.1u 16V +3.3V_ST C605 100u 16V S7_MPLL C606 0.1u 16V C552 0.1u 16V +17V 17V C634 4.7u 50V C341 68u 35V C635 4.7u 50V C344 68u 35V C636 0.01u 50V C340 0.1u 50V Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine IC605 TPA54319 +5V_TU C641 10u 16V C642 10u 16V L610 2A C304 22u 10V IC503(S-FLASH) MX25L8005M2I-15G SUB ASSY 5V_TU C307 0.1u 16V IC303 Audio AMP STA338BWG13TR LGE Internal Use Only 3-2. GP2R Power Block Diagram +5V L604 3A L605 3A +5V C621 100u 16V C624 100u 16V C628 0.1u 16V L101 2A C631 22u 16V C103 22u 10V IC206 AP2191 C223 100u 16V C104 0.1u 16V C725 10u 16V C728 0.1u 16V IC706 AZ1085S C750 0.1u 16V IC704 TPS54319 C753 22u 16V C746 10u 10V C747 10u 10V L708 2A C754 0.1u 16V L709 2A C748 0.1u 16V L710 2A 0.1u 16V +3.3V_3D IC707 AZ1117ST C752 C751 0.1u 16V 22u 16V L705 2A C789 10u 16V C753 10u 16V L706 2A L707 2A C658 0.1u 16V IC606 AZ1085S C659 22u 6.3V C660 0.1u 16V L601 2A C661 0.1u 16V C126 0.1u 16V L100 2A 1.0V C735 0.1u 16V R834 0Ω1/10W C805 100p 50V C754 100p 50V SPDIF 1.0V_LTX 13ea C755 0.1u 16V IC205 AT24C02 EDID USB C222 0.1u 16V C235 0.1u 16V L708 2A +5V_CI_ON 0.1u 16V 0.1u 16V 7ea 0.1u 16V 7ea 0.1u 16V 3ea 33ea IC702 MX25L4005 1.8V 3.3V_LTX 3.3V_VDD 3.3V_PLL +3.3V_CI C128 0.1u 16V C120 0.1u 16V C332 0.1u 50V IC101 74LCX244 IC303 Audio AMP +3.3V_TU L300 2A C309 22u 10V Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine +3.3V_TU C302 0.1u 16V C313 0.1u 16V IC301 AZ1117H +1.2V_TU C325 22u 10V C322 0.1u 16V C300 0.1u 16V +1.2V_TU LGE Internal Use Only 3-3. LDO/DC-DC Start up ■ IC600 (+3.3V_AVDD/AZ1085S) ■ IC602 (+1.5V_DDR_IN/TPS54319) Vin Vout Vin Ve n Vo Io ■ IC604(+2.5V_AVDD/TJ3964S) ■ IC603 (+1.26V_VDDC/TPS54319) Vin Vout Vin Ve n Vo Io Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 3-4. LDO/DC-DC Start up ■ IC606 (+3.3V/AZ1085S) Vout Vin ■ IC605 (+5V_TU/TPS54231) Vin Ve n Vo Io Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 3-5. GP2R I2C MAP +5V_HD MI DDCR_CK/GPIO72 DDCR_DA/GPIO71 DDC_SCL/SDA_1~3 1 (R208,209) 2 (R233,234) 10K 3 (R256,257) (N22)<I2C-SCL> (M22)<I2C-SDA> EEPROM EEPROM 0xA0 0xA0 Ch2 Ch2 HDMI1,2,3 HDMI1,2,3 0xA0 0xA0 Ch10,12,11 Ch10,12,11 TGPIO2/I2C_CLK TGPIO3/I2C_SDA <EEPROM-SCL>+3.3 <EEPROM-SDA> V 2.2K (R480,R482) (R3) <TU_SCL> (T3) <TU_SDA> HDCP HDCP EEPROM EEPROM 0xA8 0xA8 Ch2 Ch2 4.7K (R319,R326) <SCL1>+3.3V_T <SDA1> TUNER TUNER TDTJ-S001D TDTJ-S001D 0x10/C2 0x10/C2 Ch6 Ch6 SATURN7R SATURN7R TGPIO0/UPGAIN +3.3V_S T SUB_SCL SUB_SDA (F15)I2S_IN_WS/GPIO174 (F14)I2S_IN_BCK/GPIO175 TGPIO1/DNGAIN (U1) (U2) AMP AMP STA338BWG13TR STA338BWG13TR 0x38 0x38 Ch5 Ch5 4.7K (R635,R633) TOUCH TOUCH 0x52 0x52 Ch7 Ch7 G_EYE G_EYE 0x20 0x20 Ch7 Ch7 I2S_IN_SD/GPIO176 SPDIF_IN/GPIO177 DDCA_DA/UART0_TX Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine +3.3 V +3.3 (F13)<P_SCL> <MODULE_SCL/3DF_SCL> 4.7K (R780,R781) <MODULE_SDA/3DF_SDA> (G14)<P_SDA> 3.3K (R1412,R1411) V_A VDD LG8300 MODULE LG8300 MODULE 0x74 0x74 Ch4 Ch4 DDCA_CK/UART0_RX <AMP_SCL> <AMP_SDA> 2K (R360,R359) (B5) <RGB_DDC_SCL> (A5) <RGB_DDC_SDA> 0x1C 0x1C Ch4 Ch4 10K (R237,R247) EEPROM EEPROM RGB RGB 0xA0 0xA0 Ch8 Ch8 +5.0 <DDC_SCL/UART_RX> <DDC_SDA/UART_TX> V_ST ISP ISP LGE Internal Use Only 4. LM1 Power Block optimization. 1. GP2R vs LM1 Power Block. Amp 17V 17V 5V Tuner TPS54231 2A 5.1V 1.25V Tuner LDO 3.3V 3D LDO (3A) 1.8V 3D DDR LDO 1V 3D core AOZ1073 3A FET SW St 5V 3.3V Standby LDO(AP2121) 3.3V AVDD LDO (3A) LDO : 7 1.25V _TU LDO (1A) 2.5V LDO (1A) 5.1V 2.5V LDO AP2191 USB 1.24V core 1.5V DDR TPS65253(3A) 1.5V DDR AOZ1073 3A 1.26V Core AOZ1073 3A DC/DC : 4 1.8V Tuner LDO (1A) 3.3V Multi TPS54327(3A) AP2191 USB 3.3V Multi LDO (3A) Amp 3.5V St. 3.3V ST AP2121 DC/DC : 2 GP2R Power Block Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LDO : 4 LM1 Power Block LGE Internal Use Only 4-1. P_17V Spec) 850mV↓ 16mVrms 17V to 3.3V 283mVpp C620 C621 10uF 0.1uF 25V 50V 3216 2012 TPS54327 (3A, $0.14) +3.3V L605 2.2uH +3.3V_CI Spec) 165mV ↓ 4.7mVrms 46.6mVpp L101 120 Ohm 3.5A C629/50 C630 2A C137 4.9x4.9 10uF 0.1uF 1608 0.1uF 16V →6.3V 3216 →1608 0.00586↓ 16V 16V 1005 1005 OP-Amp for SC 1 7 V Spec) 165mV ↓ 8.66mVrms 37.5mVpp Buffer for CI_ADDR [0:7] change C667 C668 0.1uF 68uF 50V 35V 1608 8PI/6.3H C693 C694 10uF 0.01uF Audio AMP +3.3V_TU Spec) 165mV ↓ 13.5mVrms 158mVpp L604 120 Ohm 17V to 12V TPS54231D (2A) 2A C627 1608 10uF 3.3V to 1.8V AP1117E18G (850mW) Spec) 90mV↓ 4.6mVrms 41.6mVpp C631 C618 10uF 0.1uF 6.3V 6.3V 16V 1608 Spec) 165mV↓ 23.4mVrms 166.6mVpp 1608 1005 25V 50V C614 C615 3225 1005 0.1uF 10uF 16V 16V →6.3V 3216 →1608 change C643 0.1uF C711 C712 10uF 0.1uF 16V 50V 3216 1608 LNB 50V 1608 Audio AMP Spec) 165mV↓ 8.5mVrms 186.6mVpp 1005 Tuner C638 C646 0.1uF 50V 1608 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 4-2. P_17V * Y17 +2.5V +3.3V Spec) 165mV↓ 7.8mVrms 47.5mVpp x3 C605 3.3V to 2.5V TJ3940S-2.5V (714mW) 10uF 120 Ohm L613 LM1 120 Ohm C612 2A C1417 x6 2A C682 C671 10uF 1608 10uF 0.1uF 1608 0.1uF 10uF 16V 16V 1005 1005 10V →6.3V 2012 →1608 change 6.3V 6.3V 1608 1608 10V →6.3V 2012 →1608 change Tuner DVB_T2 1 7 V * W18/9 Spec) 165mV↓ 9.7mVrms 67.5mVpp L408/9 120 Ohm 2A x5 X4 1608 0.1uF 10uF 16V 10V →6.3V 2012 →1608 change 1005 x3 C554 0.1uF 10uF 16V 10V →6.3V 2012 →1608 change 1005 LM1 +1.25V_TU 3.3V to 1.25V AP1117EG-13 (???mW) C625 10uF 6.3V 1608 HDCP C427 0.1uF 10uF 16V 10V →6.3V 2012 →1608 0.00636↓ 1005 Nand Flash x2 * L7 Spec) 165mV↓ 8.5mVrms 45mVpp change C552 Tuner NVR 0.1uF C684 C685 16V 0.1uF 10uF 1005 16V 6.3V 1005 1608 NOT_HNIM Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 4-3. P_5V Spec) 250mV↓ 7mVrms 70mVpp L600 120 Ohm 5A C608 C610 2012 10uF 0.1uF 10V →16V 2012 →3216 0.0005↓ +5V USB OCD 16V 1005 C219 0.1uF change 5 V SPDIF 16V 1005 +5V_CI_ON Spec) 250mV↓ 31mVrms 135.4mVpp L100 MOFET Switch 120 Ohm C100 C101 0.1uF 22uF 0.1uF 16V 10V →16V 3216 →3225 0.017↓ 2A C104 1608 1005 PCMCI 16V 1005 change Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 4-4. P_5V * M14 +1.24V_VDDC +5V L606 L405 ???mVrms 120 Ohm 120 Ohm Spec) 55mV↓ 9.4mVrms 48.3mVpp C1413 ???mVrms 5A C653/4 C683/57 2A x2 2012 10uF 22uF 1608 0.1uF 10uF 25V 16V 16V 3225 3225 1005 10V →6.3V 2012 →1608 change 5V to 1.1V TPS65253RH D (adjustable) $0.25 x3 x3 0.1uF 10uF 16V 10V →6.3V 2012 →1608 change 1005 5 V * R15 LM1 Spec) 55mV↓ 17.7mVrms 70mVpp * M17 +1.5V_DDR_IN Spec) 55mV↓ 15.9mVrms 90mVpp L412 120 Ohm C651/56 C467 2A x4 x4 22uF 1000pF 50V 1608 10uF 0.1uF 1uF 16V 16V 10V 3225 1005 10V →6.3V 2012 →1608 change 1005 1005 VCC_1.5V_DDR LM1 MIU0/1 C468 * IC501 / G7 Spec) 55mV↓ 19.69mVrms 120.8mVpp L500 500 Ohm 3A C544 C545 x2 x2 ??? 10uF 0.1uF 1000pF 0.1uF 10V →6.3V 2012 →1608 16V 50V 16V 1005 1005 1005 DDR1/2 change Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 4-5. STBY Spec) 250mV↓ 23mVrms 150mVpp C600 C601 10uF 10V →16V 2012 →3216 5V to 3.3V AP2121N-3.3 (0.3A) +3.3V_ST C604 C228 0.1uF 1uF 0.1uF 16V 6.3V 16V 1005 1005 1005 RS232C 0.0005↓ change L406 120 Ohm S T B Y 2A C469 1608 0.1uF LM1 16V 1005 C556 Serial Flash 0.1uF 16V 1005 C547 SUB Ass’y 0.1uF 16V 1005 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 4-6. GP4 LM1 I2C MAP EAX64337201_0 +3.3V_TU I2C_SCKM1/GPIO75 I2C_SDAM1/GPIO76 AE6 AD6 TU_SCL TU_SDA IC400 R3082.2K R309 2.2K TU300 TDSS-G201D +3.3V GPIO49 GPIO50 AB5 AB3 AMP_SCL AMP_SDA R624 2K R623 2K IC300 STA368BWG +3.3V_AVDD I2S_IN_WS/GPIO149 SPDIF_IN/GPIO152 D9 D7 P_SCL P_SDA R468 3.3K R466 3.3K SCL_3.3V_MOD P500 SDA_3.3V_MOD LVDS +3.3V_ST I2S_IN_SD/GPIO151 I2S_IN_BCK/GPIO150 D8 C8 SUB_SCL SUB_SDA R539 4.7K R538 4.7K P501 KEY/IR PIN8 +3.3V_AVDD I2C_SCKM2/DDCR_CK/GPIO72 I2C_SDAM2/DDCR_DA/GPIO71 P23 P24 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine I2C_SCL I2C_SDA R469 2.2K R468 2.2K IC503 EEPROM IC502 HDCP (OTP) LGE Internal Use Only 5. GP4 LM1 SOC Power Sequence Procedure ▶Hot Point 288ms / [Spec] before all pwr input raise SOC_RESET +3.3V_AVDD +1.10V_VDDC Multi_PWR 0ms +1.5V_DDR_IN SOC_RESET Threshold +3.3V_AVDD +1.10V_VDDC +1.5V_DDR_IN ◈ SOC_RESET timing and Power sequence are ok. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 5. GP4 LM1 SOC Power Sequence Procedure ◈ Solution █ Value of Capacitor and resister. ① Cap Æ 22uF. 0CK226DC67A 22uF 6.3V $0.0117 ② Resister Æ 100㏀. +3.3V_AVDD 1 Threshold SOC_RESET 2 Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 6. Memory margin test. (DDR) STEP1. Setting like below. (Red box) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine STEP2. Call “direct MIU Auto BIST” function from Menu. LGE Internal Use Only 6. Memory margin test. (DDR) STEP3. Setting like below and push “Start DQS”. (Red box) STEP4. below picture is test result. Red box is timing margin. ※Normal operating board has timing margin 7~9. If timing margin under 7 ,it’s some problem DDR or Main MIU. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 7. Pen touch overview. (Installation_Pentouch Program.) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 7. Pen touch overview. (Installation_Pentouch Program.) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 7-1. Pen touch overview. (Check the installation status.) 1 Currently installed programs Check the LG Pentouch Multi-touch Driver or Pentouch TV Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine 2 Check USB Dongle Driver in Device Manager -LG Pentouch Multi-touch Driver(MultiTouch) -LG Pentouch Multi-touch Driver(BUS) -LG Pentouch Multi-touch Driver(Dongle) the Dongle Driver should be displayed when connected USB Dongle LGE Internal Use Only 7-2. Pen touch overview. (Pairing between Touch Pen and Dongle) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 7-3. Pen touch overview. (Pairing between Touch Pen and Dongle) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 7-4. Pen touch overview. (Using the Pentouch Function) ■ Image shown may differ from your monitor. You need the following items to use the Pentouch functions: 1 Enter the Pentouch mode on your monitor. - Press TOUCH button on the remote control or MENU to access the main menus. Then choose Pentouch function. 2 Select the correct computer input connection to enter the Pentouch mode. 3 Use the touch pen or the mouse to start the Pentouch program. Pressing the /Home button on the touch pen works in the same way as right-clicking the mouse. ■ Viewing the Screen Settings I mage shown may differ from your monitor. If you press the OK button on the remote control, the screen shown below appears to indicate that the screen settings have been updated successfully. ① The text "Pentouch" should be displayed to indicate that the Pentouch mode is activated. If not, restart the Pentouch mode. ② "1365x768 " should be displayed to indicate that the resolution has been set successfully. If not, set the monitor resolution again.(See p.38) Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only 7-5. Pen touch overview. (PDP Pen Touch Concept) Principle 2. The position data processed Pentouch TV Application looks like PC mouse. Step 1. USB Dongle receive the position data. Step 2. USB Dongle Driver parsing the positon Step 3. Pentouch TV application drawing and click function. Step 4. The result was displayed PDP TV through HDMI or RGB cable. Principle 1. The Pen using PDP Cell’s light energy Step 1. The pen detect the PDP Cell’s light Step 2. The pen convert detected light to voltage Step 3. The pen calculate X,Y position Step 4. The pen transfer the X,Y data through RF Pen The photo sensor in the pen detect the light RF Wireless communication (2.4GHz) USB Dongle It can use Multi-Touch function by support 2 pens. Plasma Display Pentouch TV Application - It was developed by LG. - It can be using internet for web surfing , Flash Game etc. The HDMI or RGB signal is PC’s output that configuration set by clone mode. Copyright © 2011 LG Electronics Inc. All rights reserved. Only for training and service purposes Downloaded from www.Manualslib.com manuals search engine LGE Internal Use Only